br_immed_retired
br_mis_pred
br_mis_pred_retired
br_pred
br_retired
br_return_retired
bus_access
bus_cycles
cid_write_retired
cnt_cycles
cpu_cycles
cti_trigout4
cti_trigout5
cti_trigout6
cti_trigout7
dtlb_walk
exc_return
exc_taken
inst_retired
inst_spec
itlb_walk
l1d_cache
l1d_cache_lmiss_rd
l1d_cache_refill
l1d_cache_wb
l1d_tlb
l1d_tlb_refill
l1i_cache
l1i_cache_lmiss
l1i_cache_refill
l1i_tlb
l1i_tlb_refill
l2d_cache
l2d_cache_allocate
l2d_cache_lmiss_rd
l2d_cache_refill
l2d_cache_wb
l2d_tlb
l2d_tlb_refill
l3d_cache
l3d_cache_allocate
l3d_cache_lmiss_rd
l3d_cache_refill
ld_align_lat
ldst_align_lat
ll_cache_miss_rd
ll_cache_rd
mem_access
mem_access_checked
mem_access_checked_rd
mem_access_checked_wr
memory_error
op_retired
op_spec
remote_access
sample_collision
sample_feed
sample_filtrate
sample_pop
st_align_lat
stall
stall_backend
stall_backend_mem
stall_frontend
stall_slot
stall_slot_backend
stall_slot_frontend
trb_wrap
trcextout0
trcextout1
trcextout2
trcextout3
ttbr_write_retired