# params

name: psid
tlv_name: file_applicable_to
offset: 0x0.24
size: 0x10.0
type: STRING
description:
The PSID of the NIC that this file is applicable for. This ASCII string must be zero terminated if shorter than 16 characters.


name: psid_branch
tlv_name: file_applicable_to
offset: 0x10.24
size: 0x10.0
type: STRING
description:
The PSID-BRANCH that this file is applicable to. This ASCII string must be zero terminated if shorter than 16 characters. If PSID-Branch is not defined, the string is empty.


name: keypair_uuid
tlv_name: file_signature
offset: 0x10.24
size: 0x10.0
type: BYTES
description:
The UUID of the key-pair used for signing this file. An all zero UUID means that the signature is a SHA256 of the image.


name: auth_type
tlv_name: file_public_key
offset: 0x0.0
size: 0x0.8
type: ENUM
textual_values: INVALID_ENTRY=0x0,SHA256_DIGEST=0x1,_2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256=0x3
description:
The authentication mechanism used with this key\;0x0: INVALID_ENTRY\;0x1: SHA256_DIGEST\;0x3: _2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256


name: auth_type
tlv_name: file_public_key_4096_a
offset: 0x0.0
size: 0x0.8
type: ENUM
description:
The authentication mechanism used with this key\;0x0: INVALID_ENTRY\;0x1: SHA256_DIGEST - not supported for this Key.\;0x3: _2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256 - not supported for this Key.\;0x4: _4096BIT_RSASSA_PKCS1_v1_5_WITH_SHA512

textual_values:
INVALID_ENTRY=0x0,SHA256_DIGEST=0x1,_2048BIT_RSASSA_PKCS1_v1_5_WITH_SHA256=0x3,_4096BIT_RSASSA_PKCS1_v1_5_WITH_SHA512=0x4


name: public_key_exp
tlv_name: file_public_key_4096_a
offset: 0xC.0
size: 0x4.0
type: UNSIGNED
description:
The public key exponent.\;In most cases, the standard exponent (65537) will be used (per RFC4871).\;


name: nonce_version
tlv_name: file_device_unique
offset: 0x0.24
size: 0x0.8
type: ENUM
textual_values: b32=0x0,b76=0x1
description:
Version of challenge format.\;0x0: b32 - 32 bytes challenge (used for tokens)\;0x1: b76 - 76 bytes challenge (used for FRC)\;Other values are Reserved


name: max_power
tlv_name: nv_module_power
offset: 0x0.0
size: 0x0.8
type: BINARY
mlxconfig_name: MODULE_MAX_POWER_OVERRIDE
dependency: $nv_module_feature_cap.nv_module_power_cap==1
description:
Max consumption power allowed, from thermal perspective, for module cage.\;Please advise that change of this field value requires the suitable LFM capability.\;0x0 - Maximum power is from devices default capability\;Other - Maximum power consumption in multiples of 0.25W.\;Note: Device has upper limit of max power consumption to prevent harmful configuration


name: mac_assignment_for_lane
tlv_name: nv_module_split
offset: 0x0.24
size: 0x10.0
type: BINARY
mlxconfig_name: MODULE_SPLIT
description:
MAC number assignment for logical lane <i>.\;MAC numbering starts from value of 1.\;number of logical lanes assigned to the same MAC number will define the port width.\;Value of 0 indicates lane is on default device mapping\;Value of 0xFF indicates lane is unmapped


name: base_mac
tlv_name: nv_base_mac_guid
offset: 0x0.24
size: 0x8.0
type: BYTES
description:
The base MAC address of the device. The MAC addresses for the PCI physical functions of all the network ports are derived from the base MAC.\;Offset 00h, bits 15..0 hold bits 47..32 of the MAC address.\;Offset 04h, bits 31..0 hold bits 31..0 of the MAC address.


name: base_guid
tlv_name: nv_base_mac_guid
offset: 0x8.24
size: 0x8.0
type: BYTES
description:
The base InfiniBand GUID. The InfiniBand addresses for the PCI physical functions of all the network ports are derived from the base GUID.


name: min_allowed_fw_version
tlv_name: nv_forbidden_versions
offset: 0x8.0
size: 0x4.0
type: BINARY
description:
The minimal (earliest) firmware version priori to which the device must refuse update.\;Bits 31..24 - Major version\;bits 23..16: Minor version\;Bits 15..0 - Sub-minor version


name: forbidden_fw_version
tlv_name: nv_forbidden_versions
offset: 0x10.0
size: 0x80.0
type: BINARY
description:
A list of FW versions to which the device must refuse update. The FW version format is identical to the one shown in min_allowed_fw_version description.\;The list has up to 32 entries and is terminated by an entry set to 0x0.


name: log_memic_bar_size
tlv_name: nv_memic_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: MEMIC_BAR_SIZE
dependency: $nv_memic_cap.max_memic_size_limit!=0
max_val: $nv_memic_cap.max_log_memic_bar_size
description:
The amount of BAR size assigned for MEMIC. The size in bytes is memic_size_limit*2^log_memic_bar_size.\;When activating MEMIC Atomic access by MEMIC_ATOMIC, the allocated BAR size for MEMIC is doubled.


name: memic_size_limit
tlv_name: nv_memic_conf
offset: 0x0.8
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,_256KB=0x1,_512KB=0x2,_1024KB=0x3
mlxconfig_name: MEMIC_SIZE_LIMIT
dependency: $nv_memic_cap.max_memic_size_limit!=0
max_val: $nv_memic_cap.max_memic_size_limit
description:
The maximum amount of internal device memory that can be consumed by the MEMIC application.\;0x0: DISABLED\;0x1: _256KB\;0x2: _512KB\;0x3: _1024KB


name: memic_atomic
tlv_name: nv_memic_conf
offset: 0x0.14
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MEMIC_ATOMIC_DISABLE=0x1,MEMIC_ATOMIC_ENABLE=0x2
mlxconfig_name: MEMIC_ATOMIC
dependency: $nv_memic_cap.memic_atomic_supported==1
description:
Indicates whether Atomic operations address range is supported for MEMIC. When accessing this range Read and Write operation are translated into 'Atomic test-and-set' and 'Atomic add' respectively.\;0x0: DEVICE_DEFAULT\;0x1: MEMIC_ATOMIC_DISABLE\;0x2: MEMIC_ATOMIC_ENABLE\;other values are reserved


name: memic_atomic_endianness
tlv_name: nv_memic_conf
offset: 0x0.16
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MEMIC_ATOMIC_ENDIANNESS_BIG=0x1,MEMIC_ATOMIC_ENDIANNESS_LITTLE=0x2
mlxconfig_name: MEMIC_ATOMIC_ENDIANESS
dependency: $nv_memic_cap.memic_atomic_endianness==1
description:
Indicates what is the endianness of MEMIC for DM operations. \;This configuration does not apply to Internal CPU.\;0x0: DEVICE_DEFAULT\;0x1: MEMIC_ATOMIC_ENDIANNESS_BIG\;0x2: MEMIC_ATOMIC_ENDIANNESS_LITTLE


name: max_memic_size_limit
tlv_name: nv_memic_cap
offset: 0x0.8
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,_256KB=0x1,_512KB=0x2,_1024KB=0x3
description:
The maximum value allowed for memic_size_limit.\;0x0: DISABLED\;0x1: _256KB\;0x2: _512KB\;0x3: _1024KB


name: log_num_descriptor
tlv_name: nv_host_chaining_conf
offset: 0x4.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: HOST_CHAINING_DESCRIPTORS
description:
Log(base 2) of the number of packets descriptors that should be allocated by the host for host chaining for a given IEEE802.1p priority i.\;0 means that no descriptors are allocated for this priority and traffic with this priority will be dropped.


name: log_data_size
tlv_name: nv_host_chaining_conf
offset: 0xC.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: HOST_CHAINING_TOTAL_BUFFER_SIZE
description:
Log(base 2) of the buffer size (in bytes) allocated for host chaining for a given IEEE802.1p priority i.\;0 means no buffer for this priority and traffic with this priority will be dropped.


name: log_max_total_data_size
tlv_name: nv_host_chaining_cap
offset: 0x4.16
size: 0x0.8
type: UNSIGNED
description:
Log(base 2) of the maximal total data buffer size allocated for host chaining (sum of all priorities)


name: log_max_total_num_descriptors
tlv_name: nv_host_chaining_cap
offset: 0x4.24
size: 0x0.8
type: UNSIGNED
description:
Log2 of the maximal total number of packet descriptors allocated for host chaining (sum of all priorities).


name: internal_cpu_model
tlv_name: nv_internal_cpu_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: SEPARATED_HOST=0x0,EMBEDDED_CPU=0x1
mlxconfig_name: INTERNAL_CPU_MODEL
dependency: ignore_dependency
description:
Select the model for the Internal CPU\;0x0: SEPARATED_HOST - Supported only when NV_INTERNAL_CPU_CAP.separate_host_model_supported==1.\;0x1: EMBEDDED_CPU - Supported only when NV_INTERNAL_CPU_CAP.embedded_cpu_model_supported==1.\;other values are reserved\;This NVCONFIG parameter can only be configured from the embedded CPU.


name: page_supplier
tlv_name: nv_internal_cpu_conf
offset: 0x0.4
size: 0x0.1
type: ENUM
textual_values: ECPF=0x0,EXT_HOST_PF=0x1
mlxconfig_name: INTERNAL_CPU_PAGE_SUPPLIER
description:
Defines the owner of providing ICM pages to the external host functions\;0x0: ECPF\;0x1: EXT_HOST_PF\;Valid for INTERNAL_CPU_MODEL = EMBEDDED_CPU\;

dependency:
($nv_internal_cpu_conf.internal_cpu_model==1) && ($nv_internal_cpu_cap.host_page_supplier_supported==1)


name: esw_manager
tlv_name: nv_internal_cpu_conf
offset: 0x0.5
size: 0x0.1
type: ENUM
textual_values: ECPF=0x0,EXT_HOST_PF=0x1
mlxconfig_name: INTERNAL_CPU_ESWITCH_MANAGER
description:
Defines the owner of Eth Embedded Switch responsibilities\;0x0: ECPF\;0x1: EXT_HOST_PF\;Valid for INTERNAL_CPU_MODEL = EMBEDDED_CPU\;

dependency:
($nv_internal_cpu_conf.internal_cpu_model==1) && ($nv_internal_cpu_cap.host_esw_manager_supported==1)


name: offload_engine
tlv_name: nv_internal_cpu_conf
offset: 0x0.8
size: 0x0.1
type: ENUM
textual_values: ENABLED=0x0,DISABLED=0x1
mlxconfig_name: INTERNAL_CPU_OFFLOAD_ENGINE
description:
Defines whether the Internal CPU is used as an offload engine\;0x0: ENABLED\;0x1: DISABLED\;Valid for INTERNAL_CPU_MODEL = EMBEDDED_CPU\;

dependency:
($nv_internal_cpu_conf.internal_cpu_model==1) && ($nv_internal_cpu_cap.disable_offload_engine_supported==1)


name: flex_parser_profile_enable
tlv_name: nv_flex_parser_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: FLEX_PARSER_PROFILE_ENABLE
description:
Indicates which flex parser profile to enable. Each profile supports a set of protocols. The support indication and the set of protocols supported by profile 'x' reported in NC_FLEX_PARSER_CAP.flex_parser_profile_x_supported.

dependency:
($nv_flex_parser_cap.flex_parser_profile_0_supported==1)||($nv_flex_parser_cap.flex_parser_profile_1_supported==1)||($nv_flex_parser_cap.flex_parser_profile_2_supported==1)||($nv_flex_parser_cap.flex_parser_profile_3_supported==1)||($nv_flex_parser_cap.flex_parser_profile_4_supported==1)||($nv_flex_parser_cap.flex_parser_profile_5_supported==1)||($nv_flex_parser_cap.flex_parser_profile_6_supported==1)||($nv_flex_parser_cap.flex_parser_profile_7_supported==1)||($nv_flex_parser_cap.flex_parser_profile_8_supported==1)

rule:
($flex_parser_profile_enable==0 && $nv_flex_parser_cap.flex_parser_profile_0_supported==1) || ($flex_parser_profile_enable==1 && $nv_flex_parser_cap.flex_parser_profile_1_supported==1) || ($flex_parser_profile_enable==2 && $nv_flex_parser_cap.flex_parser_profile_2_supported==1) || ($flex_parser_profile_enable==3 && $nv_flex_parser_cap.flex_parser_profile_3_supported==1) || ($flex_parser_profile_enable==4 && $nv_flex_parser_cap.flex_parser_profile_4_supported==1) || ($flex_parser_profile_enable==5 && $nv_flex_parser_cap.flex_parser_profile_5_supported==1)|| ($flex_parser_profile_enable==6 && $nv_flex_parser_cap.flex_parser_profile_6_supported==1)|| ($flex_parser_profile_enable==7 && $nv_flex_parser_cap.flex_parser_profile_7_supported==1)|| ($flex_parser_profile_enable==8 && $nv_flex_parser_cap.flex_parser_profile_8_supported==1)


name: prog_parse_graph
tlv_name: nv_flex_parser_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PROG_PARSE_GRAPH
dependency: ($nv_flex_parser_cap.prog_parse_graph_supported==1)
description:
When TRUE, the device parse graph may be dynamically configured. The amount of programmable resources is reduced according to the amount of protocols already supported by FLEX_PARSER_PROFILE_ENABLE.


name: flex_ipv4_over_vxlan_port
tlv_name: nv_flex_parser_conf
offset: 0x8.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: FLEX_IPV4_OVER_VXLAN_PORT
dependency: ignore_dependency
description:
The UDP port for incoming IPoVxLAN traffic (non-standard).\;When set, also affects flex_vxlan_gpe_supported when enabled on same profile.\;


name: prog_parse_graph_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
When TRUE, indicated dynamic programming of the device parse graph may be enabled using PROG_ PARSE_GRAPH.


name: flex_parser_profile_9_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.22
size: 0x0.1
type: BOOL
description:
When true, profile 9 is supported and can be enabled by NV_FLEXPARSER_CONF.flex_parser_profile_enable. Enabling this profile does not provide parsing of additional protocols. Instead, it keeps all programmable parsing resources free, restricting programmable parsing resources allocation only to ECPF when in switch mode or PF.


name: flex_parser_profile_8_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When TRUE, profile 8 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_geneve_supported\;flex_geneve_tlv_option_supported


name: flex_parser_profile_7_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When TRUE, profile 7 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_geneve_supported\;flex_icmp_supported\;flex_icmpv6_supported


name: flex_parser_profile_6_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When TRUE, profile 6 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_vxlan_pad_supported (VXLAN header is padded with additional DWs according to the 8 bit next to the VNI)\;flex_icmp_supported\;flex_icmpv6_supported


name: flex_parser_profile_5_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.26
size: 0x0.1
type: BOOL
description:
When TRUE, profile 5 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;IPoIB_UD_QP


name: flex_parser_profile_4_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When TRUE, profile 4 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows no additional protocols, keeping all programmable parsing resources free


name: flex_parser_profile_3_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.28
size: 0x0.1
type: BOOL
description:
If set, indicates profile 3 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;GTP-U


name: flex_parser_profile_2_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
If set, indicates profile 2 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;flex_vxlan_gpe_supported\;flex_ipv4_over_vxlan_supported\;flex_icmp_supported\;flex_icmpv6_supported


name: flex_parser_profile_1_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
If set, indicates profile 1 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;\;flex_geneve_supported\;flex_ctrl_word_over_mpls_over_gre_supported\;flex_ctrl_word_over_mpls_over_udp_supported\;flex_geneve_tlv_option_0_supported


name: flex_parser_profile_0_supported
tlv_name: nv_flex_parser_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
If set, indicates profile 0 is supported and can be enabled by NV_FLEX_PARSER_CONF.flex_parser_profile_enable.\;Enabling this profile allows for parsing the following protocols:\;\;flex_geneve_supported\;flex_ipv4_over_vxlan_supported\;flex_ipv4_over_ip_supported\;flex_ipv6_over_ip_supported\;flex_vxlan_gpe_supported\;flex_geneve_tlv_option_0_supported


name: log_hpin_num_descriptor
tlv_name: nv_internal_hairpin_conf
offset: 0x0.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: ESWITCH_HAIRPIN_DESCRIPTORS
description:
Log(base 2) of the number of packets descriptors allocated internally for hairpin for a given IEEE802.1p priority i.\;0 means that no descriptors are allocated for this priority and traffic with this priority will be dropped.


name: log_hpin_data_size
tlv_name: nv_internal_hairpin_conf
offset: 0x8.24
size: 0x8.0
type: UNSIGNED
mlxconfig_name: ESWITCH_HAIRPIN_TOT_BUFFER_SIZE
description:
Log(base 2) of the buffer size (in bytes) allocated internally for hairpin for a given IEEE802.1p priority i.\;0 means no buffer for this priority and traffic with this priority will be dropped.


name: log_max_hpin_total_data_size
tlv_name: nv_internal_hairpin_cap
offset: 0x0.16
size: 0x0.8
type: UNSIGNED
description:
Log(base 2) of the maximal total data buffer size allocated for eswitch hairpin (sum of all priorities)


name: log_max_hpin_total_num_descriptors
tlv_name: nv_internal_hairpin_cap
offset: 0x0.24
size: 0x0.8
type: UNSIGNED
description:
Log2 of the maximal total number of packet descriptors allocated for eswitch hairpin (sum of all priorities).


name: dpu_reset_notification_enabled
tlv_name: nv_global_pci_conf
offset: 0x0.12
size: 0x0.1
type: ENUM
textual_values: DISABLED=0x0,ENABLED=0x1
mlxconfig_name: DPU_RESET_NOTIFICATION_ENABLED
dependency: $nv_global_pci_cap.dpu_reset_notification_supported == 1
description:
When set, the NIC can report PCIe errors through AER cap to all hosts it is connected to on DPU reset\panic. (If no error reporting is enabled, the DPU will not report any error.)\;0x0: DISABLED\;0x1: ENABLED


name: rshim_pf
tlv_name: nv_global_pci_conf
offset: 0x0.13
size: 0x0.1
type: ENUM
textual_values: ENABLED=0x0,DISABLED=0x1
mlxconfig_name: INTERNAL_CPU_RSHIM
dependency: $nv_global_pci_cap.disable_rshim_pf_supported == 1
description:
Defines whether an RSHIM function will be exposed (when available) to the external host.\;0x0: ENABLED\;0x1: DISABLED\;


name: per_pf_total_vf
tlv_name: nv_global_pci_conf
offset: 0x0.14
size: 0x0.1
type: BOOL
mlxconfig_name: PF_NUM_OF_VF_VALID
dependency: $nv_global_pci_cap.per_pf_total_vf_supported == 1
description:
When TRUE, the number of VFs is defined for each networking PF individually in PF_NUM_OF_VF. In case they are not defined for a PF, device defaults are used instead.\;When FALSE, the number of VFs is defined symmetrically for all PFs by NUM_OF_VFS


name: per_pf_num_vf_msix
tlv_name: nv_global_pci_conf
offset: 0x0.15
size: 0x0.1
type: BOOL
mlxconfig_name: PER_PF_NUM_VF_MSIX
description:
When set to TRUE, the VF MSI-X configuration is defined by NUM_VF_MSIX for each PF individually. In case they are not defined for a PF, device defaults are used for that PF.\;When set to FALSE, the MSI-X configuration is defined by \;NUM_VF_MSIX for all PFs.


name: non_prefetchable_pf_bar
tlv_name: nv_global_pci_conf
offset: 0x0.17
size: 0x0.1
type: BOOL
mlxconfig_name: NON_PREFETCHABLE_PF_BAR
dependency: $nv_global_pci_cap.non_prefetchable_pf_bar_supported==1
valid_bit: non_prefetchable_pf_bar_valid
description:
When set, the PF BAR prefetchable bit is cleared.\;Note: PCI switches and operation systems have dedicated quotas for non-prefetchable memory, hence, you may need to decrease log_pf_uar_bar_size to enable this feature.


name: per_pf_num_msix
tlv_name: nv_global_pci_conf
offset: 0x0.19
size: 0x0.1
type: BOOL
mlxconfig_name: PF_NUM_PF_MSIX_VALID
dependency: $nv_global_pci_cap.per_pf_num_msix_supported == 1
description:
When TRUE, the MSI-X configuration is defined by PF_NUM_PF_MSIX for each PF individually. In case they are not defined for a PF, device defaults are used.\;When FALSE, the MSI-X configuration is defined by device defaults\;Valid only when NUM_PF_MSIX_VALID is set to FALSE.


name: per_pf_num_sf
tlv_name: nv_global_pci_conf
offset: 0x0.20
size: 0x0.1
type: BOOL
mlxconfig_name: PER_PF_NUM_SF
dependency: $nv_global_pci_cap.per_pf_num_sf_supported == 1
description:
When TRUE, the SFs configuration is defined by TOTAL_SF and SF_BAR_SIZE for each PF individually. In case they are not defined for a PF, device defaults are used. \;When FALSE, the SFs configuration is defined by device defaults.\;Valid only when PF_BAR2_ENABLE is set to FALSE.


name: vf_nodnic_enable
tlv_name: nv_global_pci_conf
offset: 0x0.22
size: 0x0.1
type: BOOL
mlxconfig_name: VF_NODNIC_ENABLE
dependency: $nv_global_pci_cap.vf_nodnic_supported == 1
description:
When set to TRUE, VF has VSC Gateway exposed through PCI, and may access the NODNIC initialization segment


name: non_prefetchable_pf_bar_valid
tlv_name: nv_global_pci_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, non_prefetchable_bar field and allow_large_non_prefetchable_pf_bar overrides the default value.


name: pf_bar_size_valid
tlv_name: nv_global_pci_conf
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When set, the pf_bar_size field is valid. \;When cleared, the device uses the "factory_settings" value.


name: vf_bar_size_valid
tlv_name: nv_global_pci_conf
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, the vf_bar_size field is valid. \;When cleared, the device uses the "factory_settings" value.


name: num_pf_msix_valid
tlv_name: nv_global_pci_conf
offset: 0x0.26
size: 0x0.1
type: BOOL
mlxconfig_name: NUM_PF_MSIX_VALID
dependency: $nv_global_pci_cap.num_pf_msix_supported==1
description:
When set, the num_pf_msix field is valid. \;When cleared, the number of PF MSI-X is defined by PER_PF_NUM_MSIX


name: num_vf_msix_valid
tlv_name: nv_global_pci_conf
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When set, the num_vf_msix field is valid. \;When cleared, the device uses the "factory_settings" value.


name: full_vf_qos_valid
tlv_name: nv_global_pci_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When set, the full_vf_qos field is valid. \;When cleared, the device uses the "factory_settings" value.


name: total_vfs
tlv_name: nv_global_pci_conf
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: NUM_OF_VFS
dependency: $nv_global_pci_cap.sriov_support==1
valid_bit: sriov_valid
max_val: $nv_global_pci_cap.max_vfs_per_pf_valid==1 ? $nv_global_pci_cap.max_vfs_per_pf : 0
description:
The total number of Virtual Functions (VFs) that can be supported, for each PF.\;Valid when PF_NUM_OF_VF_VALID is FALSE

temp_vars:
$_calculatedTotalBar=($fpp_en==1?(log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar/$num_pfs - ($log_pf_uar_bar_size)^2) / $total_vfs))) : (log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar - ($log_pf_uar_bar_size)^2) / $total_vfs))))

rule:
(($nv_global_pci_cap.max_total_msix_valid==0)||($nv_global_pci_cap.max_total_msix==0)||(($num_pfs * ($num_pf_msix + $total_vfs * $num_vf_msix))<=$nv_global_pci_cap.max_total_msix)) && (($nv_global_pci_cap.max_total_bar_valid==0)||($nv_global_pci_cap.max_total_bar==0)||($sriov_en==0)||($_calculatedTotalBar<=$nv_global_pci_cap.max_total_bar))


name: num_pfs
tlv_name: nv_global_pci_conf
offset: 0x4.16
size: 0x0.8
type: UNSIGNED
mlxconfig_name: NUM_OF_PF
dependency: ignore_dependency
valid_bit: num_pfs_valid
min_val: 0
max_val: $nv_global_pci_cap.max_num_pfs
description:
Total number of Network PCIe functions (PFs) exposed by the device. In case the number of PFs cannot be equally distributed between the number of ports, the remainder of PFs will be distribute between the ports with the lower numbers. For a Multi-Host device, this number is applied to each host individually.\;Value 0 is only supported when an Emulated PCI Switch is present or another type of PF (e.g. emulated device).


name: partial_wr_cache_mode
tlv_name: nv_global_pci_conf
offset: 0x4.24
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,DISABLED=0x1,FUNCTION_BASED=0x2,ADDRESS_BASED=0x3
mlxconfig_name: PARTIAL_WRITE_CACHE_MODE
description:
Specifies the mode of operation for PCI write cache, for partial cacheline writes:\;0x0: DEVICE_DEFAULT - device default configuration\;0x1: DISABLED\;0x2: FUNCTION_BASED\;0x3: ADDRESS_BASED\;other values are reserved

dependency:
($nv_global_pci_cap.partial_wr_cache_mode_function==1) || ($nv_global_pci_cap.partial_wr_cache_mode_address==1)

rule:
(($partial_wr_cache_mode==0) || ($partial_wr_cache_mode==1) || ($partial_wr_cache_mode==2 && $nv_global_pci_cap.partial_wr_cache_mode_function==1) || ($partial_wr_cache_mode==3 && $nv_global_pci_cap.partial_wr_cache_mode_address==1))


name: pf_bar2_en
tlv_name: nv_global_pci_conf
offset: 0x4.27
size: 0x0.1
type: BOOL
mlxconfig_name: PF_BAR2_ENABLE
dependency: $nv_global_pci_cap.pf_bar2_supported == 1
description:
When TRUE, BAR2 is exposed on all external host PFs (but not on the embedded ARM PFs/ECPFs). The BAR2 size is defined by the log_pf_bar2_size.\;When FALSE, the SFs and BAR2 configurations are defined by PER_PF_NUM_SF


name: hide_port2_pf
tlv_name: nv_global_pci_conf
offset: 0x4.28
size: 0x0.1
type: BOOL
mlxconfig_name: HIDE_PORT2_PF
dependency: $nv_global_pci_cap.hide_port2_pf_supported != 0
description:
When TRUE, the device will not advertise the PFs associated with port 2, except for the Embedded CPU (ECPF) if exists. This configuration is available only when NV_PCI_CONF.ADVANCED_PCI_SETTINGS is TRUE.


name: fpp_en
tlv_name: nv_global_pci_conf
offset: 0x4.29
size: 0x0.1
type: BOOL
mlxconfig_name: FPP_EN
dependency: $nv_global_pci_cap.fpp_support==1
valid_bit: fpp_valid
description:
When this bit is cleared, the device exposes a single PCI function for both ports. When set, the device exposes one or more PCI functions for each port (this is the only mode supported by ConnectX-4 devices).


name: log_pf_uar_bar_size
tlv_name: nv_global_pci_conf
offset: 0x8.0
size: 0x0.6
type: UNSIGNED
description: Log 2 of the size of a PF"s UAR BAR in MBs.
mlxconfig_name: PF_LOG_BAR_SIZE
dependency: $nv_global_pci_cap.pf_bar_size_supported==1
valid_bit: pf_bar_size_valid
max_val: $nv_global_pci_cap.max_log_pf_uar_bar_size
temp_vars:
$_calculatedTotalBar=($fpp_en==1?(log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar/$num_pfs - ($log_pf_uar_bar_size)^2) / $total_vfs))) : (log2($nv_global_pci_cap.max_total_bar==0?1:(($nv_global_pci_cap.max_total_bar - ($log_pf_uar_bar_size)^2) / $total_vfs))))

rule:
($nv_global_pci_cap.max_total_bar_valid==0)||($nv_global_pci_cap.max_total_bar==0)||($sriov_en==0)||($_calculatedTotalBar<=$nv_global_pci_cap.max_total_bar)


name: num_pf_msix
tlv_name: nv_global_pci_conf
offset: 0x8.12
size: 0x0.10
type: UNSIGNED
description: Number of MSI-X vectors and EQs per PF.
mlxconfig_name: NUM_PF_MSIX
dependency: $nv_global_pci_cap.num_pf_msix_supported==1
valid_bit: num_pf_msix_valid
max_val: $nv_global_pci_cap.max_num_pf_msix
rule:
($nv_global_pci_cap.max_total_msix_valid==0)||($nv_global_pci_cap.max_total_msix==0)||(($num_pfs * ($num_pf_msix + $total_vfs * $num_vf_msix))<=$nv_global_pci_cap.max_total_msix)


name: max_acc_outstanding_read_byte_supported
tlv_name: nv_global_pci_cap
offset: 0x0.17
size: 0x0.1
type: BOOL
description:
When set, maximal accumulated outstanding read bytes can be limited by GLOBAL_PCI_CONF_2 max_acc_outstanding_read_byte.


name: vf_nodnic_supported
tlv_name: nv_global_pci_cap
offset: 0x0.22
size: 0x0.1
type: BOOL
description:
When TRUE, the device supports enabling a VF to have VSC Gateway exposed through PCI, and may access the NODNIC initialization segment.


name: pf_bar_size_supported
tlv_name: nv_global_pci_cap
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When set, the log_pf_uar_bar_size field is configurable and the max_log_pf_uar_bar_size field is valid.


name: vf_bar_size_supported
tlv_name: nv_global_pci_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, the log_vf_uar_bar_size field is configurable and the max_log_vf_uar_bar_size field is valid.


name: max_total_bar_valid
tlv_name: nv_global_pci_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect an NV_GLOBAL_PCI_CONF TLV if the total bar size required for all PFs and VFs is lower or equal to the number specified in the max_total_bar field below.


name: max_total_msix_valid
tlv_name: nv_global_pci_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect NV_GLOBAL_PCI_CONF TLV if the total MSIX required for all PFs and VFs is lower or equal to the number specified in the max_total_msix field below.


name: max_vfs_per_pf_valid
tlv_name: nv_global_pci_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the NIC will only respect NV_GLOBAL_PCI_CONF TLV if its total_vfs parameter is lower than or equal to the value of the max_vfs_per_pf field below.


name: max_total_bar
tlv_name: nv_global_pci_cap
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
description:
Maximum total of the MMIO space for all PFs and VFs combined, in megabytes.\;Note: if the number of PF or VF per port is not a power of 2, this parameter will also not be a power of 2.


name: log_max_payload_size
tlv_name: nv_tpt_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: AUTOMATIC=0x0,_4KB=0xc
mlxconfig_name: INT_LOG_MAX_PAYLOAD_SIZE
dependency: ignore_dependency
description:
Sets the PCIe burst size for the NIC internal Translation and Protection (TPT) mechanism.\;0x0: AUTOMATIC\;0xC: _4KB


name: pcie_credit_token_timeout
tlv_name: nv_global_pci_conf_2
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: PCIE_CREDIT_TOKEN_TIMEOUT
dependency: $nv_global_pci_cap.pcie_credit_token_timeout_supported == 1
description:
PCIe credit timeout. In case a pending transaction has no credits longer than this timeout value, buffered transactions will be dropped. Value is given in milliseconds in the range of 10 to 4,000. \;Value 0x0 indicates the device will adjust the timeout automatically.\;Value 0xffff disables the feature.\;


name: max_acc_outstanding_read_byte
tlv_name: nv_global_pci_conf_2
offset: 0x0.16
size: 0x0.16
type: UNSIGNED
mlxconfig_name: MAX_ACC_OUT_READ
description:
Maximum accumulated outstanding Read requests bytes. Value is given in units of 1K bytes.\;The limit is applied for each PCI bus link individually.\;Value 0x0 indicates the use of device defaults.\;Configuration is available only when NV_PCI_CONF.ADVANCED_PCI_SETTINGS is TRUE.

dependency:
($nv_pci_conf.advanced_pci_settings!=0) && ($nv_global_pci_cap.max_acc_outstanding_read_byte_supported==1)


name: pci_switch_lanes_remapping_en
tlv_name: nv_pci_switch_evb_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_SW_LANES_REMAPPING_EN
dependency: ignore_dependency
description:
When set allows remapping of the PCI switch lanes to slots according to the PCI_SW_LANES_MAPPING parameter.


name: pci_switch_lanes_mapping
tlv_name: nv_pci_switch_evb_conf
offset: 0x4.24
size: 0x8.0
type: BINARY
mlxconfig_name: PCI_SW_LANES_MAPPING
description:
Evaluated from the LSB, each bit represents the mapping of two PCI lanes to independent PCI buses where a value of zero indicates that the corresponding lanes are the first lanes of a new bus, and a value of 1 indicates that the corresponding lanes belongs to the same bus as the previous lanes.\;Examples:\;11111110b => all 16 lanes are mapped to the host. The actual bus width is learned dynamically so it may also be 8 or 4 lanes.\;00000000b => The host bus width is up to 2 lanes and there are additional 7 independent buses. \;11101110b => The host bus is up to 8 lanes and there is an addition bus of up to 8 lanes.


name: number_of_pci_switch_lanes
tlv_name: nv_pci_switch_evb_cap
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
description:
The number of lanes that can be configured in the PCI switch using the PCI_SW_LANES_MAPPING parameter.


name: num_port
tlv_name: nv_power_conf
offset: 0x0.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: NETWORK_PORTS_NUMBER
dependency: $nv_power_cap.max_num_port!=0
min_val: 0
max_val: $nv_power_cap.max_num_port
description:
Number of network ports enabled by the device, If the value exceeds the number of ports supported by the card, this field will be ignored. Value 0x0 indicates device defaults.


name: rt_pps_out_default
tlv_name: nv_power_conf
offset: 0x0.19
size: 0x0.1
type: BOOL
mlxconfig_name: RT_PPS_ENABLED_ON_POWERUP
dependency: ($nv_power_cap.rt_pps_out_default_supported==1)
description:
When TRUE the PPS_OUT will be activated on power up\;Applicable only when REAL_TIME_CLOCK_ENABLE is TRUE


name: lag_allocation
tlv_name: nv_power_conf
offset: 0x0.20
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,PRE_ALLOCATION=0x1
mlxconfig_name: LAG_RESOURCE_ALLOCATION
dependency: ($nv_power_cap.lag_allocation_pre==1)
description:
Defines the way resources are allocated for LAG\;0x0: DEVICE_DEFAULT\;0x1: PRE_ALLOCATION - resources are preallocated regardless of LAG activation\;using pre-allocation allows LAG activation regardless of functions state\;Other values are reserved


name: phy_cnt_delay
tlv_name: nv_power_conf
offset: 0x0.22
size: 0x0.2
type: ENUM
textual_values: DELAY_NONE=0x0,DELAY_10_SEC=0x1,DELAY_20_SEC=0x2
mlxconfig_name: PHY_COUNT_LINK_UP_DELAY
dependency: ($nv_power_cap.phy_cnt_delay_supported==1)
description:
Defines a period after Link UP where phy counters activation is delayed\;0x0: DELAY_NONE\;0x1: DELAY_10_SEC\;0x2: DELAY_20_SEC\;Other values are reserved


name: accurate_scheduler
tlv_name: nv_power_conf
offset: 0x0.24
size: 0x0.1
type: BOOL
mlxconfig_name: ACCURATE_TX_SCHEDULER
dependency: ($nv_power_cap.accurate_scheduler_supported==1)
description:
When TRUE, the device will optimize the transmit scheduler for high accuracy.\;When False, the device defaults will apply for the scheduler.


name: partial_reset
tlv_name: nv_power_conf
offset: 0x0.25
size: 0x0.1
type: BOOL
mlxconfig_name: PARTIAL_RESET_EN
dependency: $nv_power_cap.partial_reset_supported==1
description:
When set, the partial reset flow is enabled. This reset skips on resetting GPIOs, loading PLL new parameters and performing self-tests. Partial reset will be triggered only if no exceptions requiring full reset were detected (for example, if any of the boot record"s parameter had changed)


name: reset_with_host_on_errors
tlv_name: nv_power_conf
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: RESET_WITH_HOST_ON_ERRORS
dependency: ($nv_power_cap.reset_with_host_on_errors_supported==1)
description:
When set, host reset will trigger a device reset, if the device has previously detected fatal errors.


name: slot_power_limiter_dis
tlv_name: nv_power_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: DISABLE_SLOT_POWER_LIMITER
dependency: ($nv_power_conf.advanced_power_settings_en==1)&&($nv_power_cap.slot_power_limiter_supported==1)
description:
When cleared, the device is not allowed to consume more than 25W from the PCIe power rails, unless a PCI slot power limit message statesthat a new power limit is received.\;When set, the slot power limiter is disabled, and the device is allowed to consume more than 25W from the PCIe power rails.\;Note: if the power limiter is active and there is not enough power, the device will shut down the network modules.


name: advanced_power_settings_en
tlv_name: nv_power_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: ADVANCED_POWER_SETTINGS
dependency: $nv_power_cap.slot_power_limiter_supported==1
description:
Show/hide additional power settings parameters.\;Warning: Wrong power settings may cause physical damage.


name: max_num_port
tlv_name: nv_power_cap
offset: 0x0.0
size: 0x0.4
type: UNSIGNED
description:
Maximal value supported for NV_POWER_CONF.num_port. Value 0x0 indicates this field is not supported.


name: accurate_scheduler_supported
tlv_name: nv_power_cap
offset: 0x0.24
size: 0x0.1
type: BOOL
description:
When TRUE, the transmit scheduler may be optimized for high accuracy by NV_POWER_CONF.accurate_scheduler


name: idle_icmd_sem_lock_threshold
tlv_name: nv_host_sync_conf
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: IDLE_ICMD_SEM_LOCK_THRESHOLD
description:
Host will be expelled from VSEC Gateway usage if it holds the ICMD Global Semaphore, without issuing any ICMD, for a period longer than this threshold. Value is given in units of 0.1sec\;Value 0xFFFF indicates this threshold is infinite (disabled)


name: icmd_sem_lock_threshold
tlv_name: nv_host_sync_conf
offset: 0x0.16
size: 0x0.16
type: UNSIGNED
mlxconfig_name: ICMD_SEM_LOCK_THRESHOLD
description:
Host will be expelled from VSEC Gateway usage if it holds the ICMD Global Semaphore for a period longer than this threshold. Value is given in units of 0.1sec\;Value 0xFFFF indicates this threshold is infinite (disabled)


name: nvme_emu_num_msix
tlv_name: nv_emulation_nvme_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: NVME_EMULATION_NUM_MSIX
dependency: ($nv_emulation_nvme_cap.nvme_emu_supported==1)
description:
Number of MSI-X Vectors assigned for each PF/VF of the NVME emulation device. Value 0x0 will use device defaults


name: nvme_emu_log_pf_queue_depth
tlv_name: nv_emulation_nvme_conf
offset: 0x14.28
size: 0x0.4
type: UNSIGNED
mlxconfig_name: NVME_EMULATION_MAX_QUEUE_DEPTH
dependency: ($nv_emulation_nvme_cap.nvme_emu_supported==1)
max_val: ($nv_emulation_nvme_cap.nvme_emu_max_log_queue_dept_supported)
description:
Log (base 2) of the maximal queue depth of NVME Physical Functions.\;Value 0 indicates device default.


name: pci_switch
tlv_name: nv_emulation_pci_switch_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_SWITCH_EMULATION_ENABLE
dependency: ($nv_emulation_pci_switch_cap.pci_switch_supported==1)
description:
When TRUE, the device will expose a PCI switch. All PF configurations are applied on the switch downstream ports. On such case, each PF will have a different PCI device on the emulated switch. This configuration allows to expose 0 network PFs toward host


name: virtio_net_emu_vf_pci_layout
tlv_name: nv_emulation_virtio_net_conf
offset: 0x0.26
size: 0x0.2
type: ENUM
textual_values: VIRTIO_1_X=0x0,VIRTIO_TRANSITIONAL=0x1
mlxconfig_name: VIRTIO_NET_EMULATION_VF_PCI_LAYOUT
dependency: ($nv_emulation_virtio_net_cap.virtio_net_emu_pci_layout_trans_supported==1)
description:
Indicates which VIrtIO specification the PCI layout of the emulated Virtual Function(s) will follow.\;0x0: VIRTIO_1_X\;0x1: VIRTIO_TRANSITIONAL\;other values are reserved


name: virtio_net_emu_pf_pci_layout
tlv_name: nv_emulation_virtio_net_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: VIRTIO_1_X=0x0,VIRTIO_TRANSITIONAL=0x1
mlxconfig_name: VIRTIO_NET_EMULATION_PF_PCI_LAYOUT
dependency: ($nv_emulation_virtio_net_cap.virtio_net_emu_pci_layout_trans_supported==1)
description:
Indicates which VIrtIO specification the PCI layout of the emulated Physical Function(s) will follow.\;0x0: VIRTIO_1_X\;0x1: VIRTIO_TRANSITIONAL\;other values are reserved


name: virtio_net_emu_num_msix
tlv_name: nv_emulation_virtio_net_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: VIRTIO_NET_EMULATION_NUM_MSIX
dependency: ($nv_emulation_virtio_net_cap.virtio_net_emu_supported==1)
description:
Number of MSI-X Vectors assigned for each PF/VF of the VIRTIO_NET emulation device. Value 0x0 will use device defaults


name: virtio_net_emu_pci_layout_trans_supported
tlv_name: nv_emulation_virtio_net_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When TRUE, setting the PCI layout of PFs or VFs to meet VirtIO standard for transitional device is supported.


name: virtio_net_emu_max_total_vf
tlv_name: nv_emulation_virtio_net_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) supported by the device for each VIRTIO_NET emulation PF.


name: virtio_blk_emu_num_msix
tlv_name: nv_emulation_virtio_blk_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: VIRTIO_BLK_EMULATION_NUM_MSIX
dependency: ($nv_emulation_virtio_blk_cap.virtio_blk_emu_supported==1)
description:
Number of MSI-X Vectors assigned for each PF/VF of the VIRTIO_BLK emulation device. Value 0x0 will use device defaults


name: virtio_blk_emu_max_total_vf
tlv_name: nv_emulation_virtio_blk_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) supported by the device for each VIRTIO_BLK emulation PF.


name: bus1_speed
tlv_name: nv_global_pci_conf_3
offset: 0x0.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
mlxconfig_name: PCI_BUS1_RESTRICT_SPEED
dependency: $nv_global_pci_cap_3.bus1_restrict_en == 1
valid_bit: bus1_restrict
max_val: $nv_global_pci_cap_3.bus1_speed_max
description:
See PCI_BUS0_RESTRICT_SPEED\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5


name: bus0_speed
tlv_name: nv_global_pci_conf_3
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
mlxconfig_name: PCI_BUS0_RESTRICT_SPEED
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
valid_bit: bus0_restrict
max_val: $nv_global_pci_cap_3.bus0_speed_max
description:
Restricts the PCI speed to be smaller or equal to:\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;Valid when PCI_BUS_RESTRICT is TRUE.


name: bus0_width
tlv_name: nv_global_pci_conf_3
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: PCI_X1=0x0,PCI_X2=0x1,PCI_X4=0x2,PCI_X8=0x3,PCI_X16=0x4
mlxconfig_name: PCI_BUS0_RESTRICT_WIDTH
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
valid_bit: bus0_restrict
max_val: $nv_global_pci_cap_3.bus0_width_max
description:
Restricts the PCI bus width to be smaller or equal to:\;0x0: PCI_X1\;0x1: PCI_X2\;0x2: PCI_X4\;0x3: PCI_X8\;0x4: PCI_X16\;Valid when PCI_BUS_RESTRICT is TRUE.


name: bus0_restrict
tlv_name: nv_global_pci_conf_3
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCI_BUS0_RESTRICT
dependency: $nv_global_pci_cap_3.bus0_restrict_en == 1
description:
When TRUE, PCI bus width, speed and ASPM will be restricted according to PCI_BUS_RESTRICT_WIDTH, PCI_BUS_RESTRICT_SPEED, PCI_BUS_RESTRICT_ASPM respectively


name: dport_owner
tlv_name: nv_global_pci_conf_3
offset: 0x10.24
size: 0x10.0
type: ENUM
mlxconfig_name: PCI_DOWNSTREAM_PORT_OWNER
description:
Identifies the owner of the respective PCI Downstream Port.\;0x0: DEVICE_DEFAULT\;0x1: HOST_0\;0x2: HOST_1\;0x3: HOST_2\;0x4: HOST_3\;0x5: HOST_4\;0x6: HOST_5\;0x7: HOST_6\;0x8: HOST_7\;0xF: EMBEDDED_CPU\;Other values are reserved

textual_values:
DEVICE_DEFAULT=0x0,HOST_0=0x1,HOST_1=0x2,HOST_2=0x3,HOST_3=0x4,HOST_4=0x5,HOST_5=0x6,HOST_6=0x7,HOST_7=0x8,EMBEDDED_CPU=0xf


name: virtio_fs_emu_num_msix
tlv_name: nv_emulation_virtio_fs_conf
offset: 0x14.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: VIRTIO_FS_EMULATION_NUM_MSIX
dependency: ($nv_emulation_virtio_fs_cap.virtio_fs_emu_supported==1)
description:
Number of MSI-X Vectors assigned for each PF/VF of the VIRTIO_FS emulation device. Value 0x0 will use device defaults


name: virtio_fs_emu_max_total_vf
tlv_name: nv_emulation_virtio_fs_cap
offset: 0x4.0
size: 0x0.16
type: UNSIGNED
description:
Maximal number of PCIe virtual functions (VFs) supported by the device for each VIRTIO_FS emulation PF.


name: secondary_pcore_host
tlv_name: nv_global_pci_conf_4
offset: 0x0.21
size: 0x0.2
type: ENUM
textual_values: HOST_1=0x0,HOST_2=0x1,HOST_4=0x2,HOST_8=0x3
mlxconfig_name: STRAP_SECONDARY_PCORE_HOSTS1
dependency: ignore_dependency
valid_bit: strap_cfg_enable
description:
Number of hosts on the secondary PCORE (matches 2nd_ PCORE_ PART0 and 2nd_ PCORE_ PART1 strap options)\;0x0: HOST_1\;0x1: HOST_2\;0x2: HOST_4\;0x3: HOST_8\;Valid only for asymmetric configurations (STRAP_ASYMMETRIC_PCORE set to TRUE)


name: sd_or_mh
tlv_name: nv_global_pci_conf_4
offset: 0x0.25
size: 0x0.1
type: BOOL
mlxconfig_name: STRAP_SD_OR_MH
dependency: ignore_dependency
valid_bit: strap_cfg_enable
description:
If TRUE, each bus is associated with a unique host (Multi-Host), otherwise it is a Socket-Direct confguration


name: strap_cfg_enable
tlv_name: nv_global_pci_conf_4
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
If TRUE, the Soft Straps configuration is enforced. Otherwise the straps configuration of lower hierarchy takes precedence


name: bus01_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x10.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS01_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus01_cfg_enable
description:
Defines PCI Bus 01 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus01_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x10.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS01_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus01_cfg_enable
description:
Bus 01 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus01_speed
tlv_name: nv_global_pci_conf_4
offset: 0x10.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS01_SPEED
dependency: ignore_dependency
valid_bit: bus01_cfg_enable
description:
PCI bus 01 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus01_width
tlv_name: nv_global_pci_conf_4
offset: 0x10.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS01_WIDTH
dependency: ignore_dependency
valid_bit: bus01_cfg_enable
description:
PCI bus 01 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus00_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x10.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS00_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus00_cfg_enable
description:
Defines PCI Bus 00 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus00_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x10.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS00_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus00_cfg_enable
description:
Bus 00 Pointer to a PCIe Switch (Switch0, Switch1, Switch2)\;Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus00_speed
tlv_name: nv_global_pci_conf_4
offset: 0x10.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS00_SPEED
dependency: ignore_dependency
valid_bit: bus00_cfg_enable
description:
PCI bus 00 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus00_width
tlv_name: nv_global_pci_conf_4
offset: 0x10.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS00_WIDTH
dependency: ignore_dependency
valid_bit: bus00_cfg_enable
description:
PCI bus 00 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus03_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x14.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS03_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus03_cfg_enable
description:
Defines PCI Bus 03 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus03_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x14.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS03_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus03_cfg_enable
description:
Bus 03 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus03_speed
tlv_name: nv_global_pci_conf_4
offset: 0x14.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS03_SPEED
dependency: ignore_dependency
valid_bit: bus03_cfg_enable
description:
PCI bus 03 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus03_width
tlv_name: nv_global_pci_conf_4
offset: 0x14.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS03_WIDTH
dependency: ignore_dependency
valid_bit: bus03_cfg_enable
description:
PCI bus 03 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus02_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x14.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS02_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus02_cfg_enable
description:
Defines PCI Bus 02 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus02_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x14.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS02_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus02_cfg_enable
description:
Bus 02 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus02_speed
tlv_name: nv_global_pci_conf_4
offset: 0x14.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS02_SPEED
dependency: ignore_dependency
valid_bit: bus02_cfg_enable
description:
PCI bus 02 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus02_width
tlv_name: nv_global_pci_conf_4
offset: 0x14.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS02_WIDTH
dependency: ignore_dependency
valid_bit: bus02_cfg_enable
description:
PCI bus 02 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus05_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x18.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS05_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus05_cfg_enable
description:
Defines PCI Bus 05 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus05_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x18.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS05_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus05_cfg_enable
description:
Bus 05 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus05_speed
tlv_name: nv_global_pci_conf_4
offset: 0x18.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS05_SPEED
dependency: ignore_dependency
valid_bit: bus05_cfg_enable
description:
PCI bus 05 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus05_width
tlv_name: nv_global_pci_conf_4
offset: 0x18.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS05_WIDTH
dependency: ignore_dependency
valid_bit: bus05_cfg_enable
description:
PCI bus 05 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus04_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x18.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS04_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus04_cfg_enable
description:
Defines PCI Bus 04 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus04_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x18.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS04_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus04_cfg_enable
description:
Bus 04 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus04_speed
tlv_name: nv_global_pci_conf_4
offset: 0x18.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS04_SPEED
dependency: ignore_dependency
valid_bit: bus04_cfg_enable
description:
PCI bus 04 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus04_width
tlv_name: nv_global_pci_conf_4
offset: 0x18.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS04_WIDTH
dependency: ignore_dependency
valid_bit: bus04_cfg_enable
description:
PCI bus 04 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus07_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x1C.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS07_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus07_cfg_enable
description:
Defines PCI Bus 07 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus07_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x1C.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS07_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus07_cfg_enable
description:
Bus 07 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus07_speed
tlv_name: nv_global_pci_conf_4
offset: 0x1C.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS07_SPEED
dependency: ignore_dependency
valid_bit: bus07_cfg_enable
description:
PCI bus 07 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus07_width
tlv_name: nv_global_pci_conf_4
offset: 0x1C.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS07_WIDTH
dependency: ignore_dependency
valid_bit: bus07_cfg_enable
description:
PCI bus 07 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus06_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x1C.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS06_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus06_cfg_enable
description:
Defines PCI Bus 06 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus06_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x1C.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS06_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus06_cfg_enable
description:
Bus 06 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus06_speed
tlv_name: nv_global_pci_conf_4
offset: 0x1C.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS06_SPEED
dependency: ignore_dependency
valid_bit: bus06_cfg_enable
description:
PCI bus 06 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus06_width
tlv_name: nv_global_pci_conf_4
offset: 0x1C.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS06_WIDTH
dependency: ignore_dependency
valid_bit: bus06_cfg_enable
description:
PCI bus 06 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus11_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x20.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS11_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus11_cfg_enable
description:
Defines PCI Bus 11 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus11_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x20.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS11_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus11_cfg_enable
description:
Bus 11 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus11_speed
tlv_name: nv_global_pci_conf_4
offset: 0x20.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS11_SPEED
dependency: ignore_dependency
valid_bit: bus11_cfg_enable
description:
PCI bus 11 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus11_width
tlv_name: nv_global_pci_conf_4
offset: 0x20.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS11_WIDTH
dependency: ignore_dependency
valid_bit: bus11_cfg_enable
description:
PCI bus 11 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus10_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x20.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS10_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus10_cfg_enable
description:
Defines PCI Bus 10 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus10_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x20.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS10_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus10_cfg_enable
description:
Bus 10 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus10_speed
tlv_name: nv_global_pci_conf_4
offset: 0x20.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS10_SPEED
dependency: ignore_dependency
valid_bit: bus10_cfg_enable
description:
PCI bus 10 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus10_width
tlv_name: nv_global_pci_conf_4
offset: 0x20.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS10_WIDTH
dependency: ignore_dependency
valid_bit: bus10_cfg_enable
description:
PCI bus 10 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus13_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x24.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS13_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus13_cfg_enable
description:
Defines PCI Bus 13 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus13_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x24.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS13_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus13_cfg_enable
description:
Bus 13 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus13_speed
tlv_name: nv_global_pci_conf_4
offset: 0x24.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS13_SPEED
dependency: ignore_dependency
valid_bit: bus13_cfg_enable
description:
PCI bus 13 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus13_width
tlv_name: nv_global_pci_conf_4
offset: 0x24.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS13_WIDTH
dependency: ignore_dependency
valid_bit: bus13_cfg_enable
description:
PCI bus 13 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus12_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x24.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS12_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus12_cfg_enable
description:
Defines PCI Bus 12 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus12_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x24.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS12_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus12_cfg_enable
description:
Bus 12 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus12_speed
tlv_name: nv_global_pci_conf_4
offset: 0x24.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS12_SPEED
dependency: ignore_dependency
valid_bit: bus12_cfg_enable
description:
PCI bus 12 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus12_width
tlv_name: nv_global_pci_conf_4
offset: 0x24.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS12_WIDTH
dependency: ignore_dependency
valid_bit: bus12_cfg_enable
description:
PCI Bus 12 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus15_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x28.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS15_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus15_cfg_enable
description:
Defines PCI Bus 15 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus15_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x28.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS15_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus15_cfg_enable
description:
Bus 15 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus15_speed
tlv_name: nv_global_pci_conf_4
offset: 0x28.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS15_SPEED
dependency: ignore_dependency
valid_bit: bus15_cfg_enable
description:
PCI bus 15 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus15_width
tlv_name: nv_global_pci_conf_4
offset: 0x28.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS15_WIDTH
dependency: ignore_dependency
valid_bit: bus15_cfg_enable
description:
PCI bus 15 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus14_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x28.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS14_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus14_cfg_enable
description:
Defines PCI Bus 14 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus14_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x28.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS14_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus14_cfg_enable
description:
Bus 14 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus14_speed
tlv_name: nv_global_pci_conf_4
offset: 0x28.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS14_SPEED
dependency: ignore_dependency
valid_bit: bus14_cfg_enable
description:
PCI bus 14 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus14_width
tlv_name: nv_global_pci_conf_4
offset: 0x28.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS14_WIDTH
dependency: ignore_dependency
valid_bit: bus14_cfg_enable
description:
PCI Bus 14 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus17_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x2C.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS17_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus17_cfg_enable
description:
Defines PCI Bus 17 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus17_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x2C.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS17_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus17_cfg_enable
description:
Bus 17 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus17_speed
tlv_name: nv_global_pci_conf_4
offset: 0x2C.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS17_SPEED
dependency: ignore_dependency
valid_bit: bus17_cfg_enable
description:
PCI bus 17 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus17_width
tlv_name: nv_global_pci_conf_4
offset: 0x2C.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS17_WIDTH
dependency: ignore_dependency
valid_bit: bus17_cfg_enable
description:
PCI bus 17 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus16_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x2C.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS16_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus16_cfg_enable
description:
Defines PCI Bus 16 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus16_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x2C.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS16_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus16_cfg_enable
description:
Bus 16 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus16_speed
tlv_name: nv_global_pci_conf_4
offset: 0x2C.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS16_SPEED
dependency: ignore_dependency
valid_bit: bus16_cfg_enable
description:
PCI bus 16 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus16_width
tlv_name: nv_global_pci_conf_4
offset: 0x2C.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS16_WIDTH
dependency: ignore_dependency
valid_bit: bus16_cfg_enable
description:
PCI bus 16 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus21_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x30.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS21_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus21_cfg_enable
description:
Defines PCI Bus 21 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus21_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x30.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS21_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus21_cfg_enable
description:
Bus 21 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus21_speed
tlv_name: nv_global_pci_conf_4
offset: 0x30.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS21_SPEED
dependency: ignore_dependency
valid_bit: bus21_cfg_enable
description:
PCI bus 21 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus21_width
tlv_name: nv_global_pci_conf_4
offset: 0x30.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS21_WIDTH
dependency: ignore_dependency
valid_bit: bus21_cfg_enable
description:
PCI bus 21 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus20_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x30.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS20_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus20_cfg_enable
description:
Defines PCI Bus 20 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus20_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x30.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS20_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus20_cfg_enable
description:
Bus 20 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus20_speed
tlv_name: nv_global_pci_conf_4
offset: 0x30.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS20_SPEED
dependency: ignore_dependency
valid_bit: bus20_cfg_enable
description:
PCI bus 20 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus20_width
tlv_name: nv_global_pci_conf_4
offset: 0x30.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS20_WIDTH
dependency: ignore_dependency
valid_bit: bus20_cfg_enable
description:
PCI bus 20 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus23_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x34.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS23_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus23_cfg_enable
description:
Defines PCI Bus 23 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus23_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x34.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS23_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus23_cfg_enable
description:
Bus 23 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus23_speed
tlv_name: nv_global_pci_conf_4
offset: 0x34.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS23_SPEED
dependency: ignore_dependency
valid_bit: bus23_cfg_enable
description:
PCI bus 23 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus23_width
tlv_name: nv_global_pci_conf_4
offset: 0x34.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS23_WIDTH
dependency: ignore_dependency
valid_bit: bus23_cfg_enable
description:
PCI bus 23 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus22_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x34.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS22_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus22_cfg_enable
description:
Defines PCI Bus 22 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus22_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x34.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS22_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus22_cfg_enable
description:
Bus 22 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus22_speed
tlv_name: nv_global_pci_conf_4
offset: 0x34.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS22_SPEED
dependency: ignore_dependency
valid_bit: bus22_cfg_enable
description:
PCI bus 22 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus22_width
tlv_name: nv_global_pci_conf_4
offset: 0x34.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS22_WIDTH
dependency: ignore_dependency
valid_bit: bus22_cfg_enable
description:
PCI Bus 22 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus25_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x38.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS25_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus25_cfg_enable
description:
Defines PCI Bus 25 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus25_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x38.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS25_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus25_cfg_enable
description:
Bus 25 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus25_speed
tlv_name: nv_global_pci_conf_4
offset: 0x38.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS25_SPEED
dependency: ignore_dependency
valid_bit: bus25_cfg_enable
description:
PCI bus 25 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus25_width
tlv_name: nv_global_pci_conf_4
offset: 0x38.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS25_WIDTH
dependency: ignore_dependency
valid_bit: bus25_cfg_enable
description:
PCI bus 25 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus24_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x38.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS24_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus24_cfg_enable
description:
Defines PCI Bus 24 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus24_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x38.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS24_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus24_cfg_enable
description:
Bus 24 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus24_speed
tlv_name: nv_global_pci_conf_4
offset: 0x38.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS24_SPEED
dependency: ignore_dependency
valid_bit: bus24_cfg_enable
description:
PCI bus 24 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus24_width
tlv_name: nv_global_pci_conf_4
offset: 0x38.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS24_WIDTH
dependency: ignore_dependency
valid_bit: bus24_cfg_enable
description:
PCI bus 24 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus27_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x3C.0
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS27_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus27_cfg_enable
description:
Defines PCI Bus 27 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus27_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x3C.2
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS27_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus27_cfg_enable
description:
Bus 27 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus27_speed
tlv_name: nv_global_pci_conf_4
offset: 0x3C.8
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS27_SPEED
dependency: ignore_dependency
valid_bit: bus27_cfg_enable
description:
PCI bus 27 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus27_width
tlv_name: nv_global_pci_conf_4
offset: 0x3C.12
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS27_WIDTH
dependency: ignore_dependency
valid_bit: bus27_cfg_enable
description:
PCI bus 27 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: bus26_pcie_hierarchy_type
tlv_name: nv_global_pci_conf_4
offset: 0x3C.16
size: 0x0.2
type: ENUM
textual_values: PCIE_ENDPOINT=0x0,PCIE_EXTERNAL_HOST_SWITCH=0x1,PCIE_INTERNAL_HOST_SWITCH=0x2
mlxconfig_name: PCI_BUS26_HIERARCHY_TYPE
dependency: ignore_dependency
valid_bit: bus26_cfg_enable
description:
Defines PCI Bus 26 connectivity hierarchy\;0x0: PCIE_ENDPOINT - PCI link connected to external host, Device is EP\;0x1: PCIE_EXTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to external host\;0x2: PCIE_INTERNAL_HOST_SWITCH - PCI links connected to an internal switch, upstream link connected to internal host


name: bus26_pcie_switch_index
tlv_name: nv_global_pci_conf_4
offset: 0x3C.18
size: 0x0.2
type: UNSIGNED
mlxconfig_name: PCI_BUS26_SWITCH_INDEX
dependency: ignore_dependency
valid_bit: bus26_cfg_enable
description:
Bus 26 Pointer to a Pcie Switch (switch0, switch1, switch2) Valid only for Hierarchy Type PCIE_HIER_TYPE_EXTERNAL_HOST_SWITCH


name: bus26_speed
tlv_name: nv_global_pci_conf_4
offset: 0x3C.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4,PCI_GEN_6=0x5
mlxconfig_name: PCI_BUS26_SPEED
dependency: ignore_dependency
valid_bit: bus26_cfg_enable
description:
PCI bus 26 speed\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5\;0x5: PCI_GEN_6


name: bus26_width
tlv_name: nv_global_pci_conf_4
offset: 0x3C.28
size: 0x0.3
type: ENUM
textual_values: PCI_INACTIVE=0x0,PCI_X1=0x1,PCI_X2=0x2,PCI_X4=0x3,PCI_X8=0x4,PCI_X16=0x5
mlxconfig_name: PCI_BUS26_WIDTH
dependency: ignore_dependency
valid_bit: bus26_cfg_enable
description:
PCI bus 26 width:\;0x0: PCI_INACTIVE\;0x1: PCI_X1\;0x2: PCI_X2\;0x3: PCI_X4\;0x4: PCI_X8\;0x5: PCI_X16


name: switch1_upstream_port_bus_index
tlv_name: nv_global_pci_conf_4
offset: 0x40.2
size: 0x0.4
type: UNSIGNED
mlxconfig_name: PCI_SWITCH1_UPSTRAEM_PORT_BUS
dependency: ignore_dependency
valid_bit: switch1_cfg_enable
description:
Index of the bus (i.e. - the 1st logic lane in the PEX of the respective bus) on which the upstream port belonging to Switch1 resides


name: switch0_upstream_port_bus_index
tlv_name: nv_global_pci_conf_4
offset: 0x40.18
size: 0x0.4
type: UNSIGNED
mlxconfig_name: PCI_SWITCH0_UPSTRAEM_PORT_BUS
dependency: ignore_dependency
valid_bit: switch0_cfg_enable
description:
Index of the bus (i.e. - the 1st logic lane in the PEX of the respective bus) on which the upstream port belonging to Switch0 resides


name: switch2_upstream_port_bus_index
tlv_name: nv_global_pci_conf_4
offset: 0x44.18
size: 0x0.4
type: UNSIGNED
mlxconfig_name: PCI_SWITCH2_UPSTRAEM_PORT_BUS
dependency: ignore_dependency
valid_bit: switch2_cfg_enable
description:
Index of the bus (i.e. - the 1st logic lane in the PEX of the respective bus) on which the upstream port belonging to Switch2 resides


name: nvia_nvconfig_on_boot
tlv_name: nv_debug_mode
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
Debug only.\;When set, firmware invalidates all NVCONFIG parameters on boot including this parameter.


name: uefi_aip_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.21
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI AIP protocols over the controller. Otherwise, UEFI driver should load UEFI AIP protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: uefi_fmp_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.22
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI FMP protocols over the controller. Otherwise, UEFI driver should load UEFI FMP protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: uefi_hii_over_ctrl
tlv_name: nv_rom_ini
offset: 0x0.23
size: 0x0.1
type: BOOL
dependency: ($nv_rom_cap.uefi_proto_over_ctrl==1)
description:
When set to TRUE, UEFI driver should load UEFI HII protocols over the controller. Otherwise, UEFI driver should load UEFI HII protocols over the child. \;Valid if NV_ROM_CAP.uefi_proto_over_ctrl is TRUE


name: dhcp_user_class
tlv_name: nv_rom_ini
offset: 0x4.24
size: 0x8.0
type: UNSIGNED
description:
DHCP user class option (RFC3004) for Flexboot.\;Octet #1 must be equal for 77d.\;octet #2 - length\;


name: hii_type
tlv_name: nv_rom_ini
offset: 0xC.16
size: 0x0.4
type: ENUM
textual_values: MLNX_DEFAULT=0x0,HPE=0x1,LENOVO=0x2,DELL=0x3,FUJITSU=0x4
description:
Type of vfr type with HII configuration selector:\;0x0: MLNX_DEFAULT\;0x1: HPE\;0x2: LENOVO\;0x3: DELL\;0x4: FUJITSU


name: hii_mriname2
tlv_name: nv_rom_ini
offset: 0xC.20
size: 0x0.1
type: BOOL
description:
Expose MRI_NAME2 field in HII with hard coded value of "Mellanox Network Adapter, physical ports $p, Logical ports 1" per Lenovo"s HII spec


name: legacy_boot_wo_failover_supported
tlv_name: nv_rom_cap
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, FlexBoot supports configuration of boot protocol, without failover to another protocol upon failure (NV_ROM_BOOT_CONF1.legacy_boot_protocol).


name: boot_ip_ver
tlv_name: nv_rom_cap
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
This bit is set when flexboot supports configuration of PXE boot IP version defined in boot settings ext parameter


name: cqe_compression
tlv_name: nv_sw_offload_conf
offset: 0x0.0
size: 0x0.3
type: ENUM
textual_values: BALANCED=0x0,AGGRESSIVE=0x1
mlxconfig_name: CQE_COMPRESSION
dependency: ignore_dependency
description:
Configure which algorithm should be used by the NIC in order to decide when to activate CQE compression based on PCIe bus condition. Note that the driver can enable compression on a per CQE basis\;0x0: BALANCED\;0x1: AGGRESSIVE


name: ip_over_vxlan_en
tlv_name: nv_sw_offload_conf
offset: 0x0.4
size: 0x0.1
type: BOOL
mlxconfig_name: IP_OVER_VXLAN_EN
dependency: $nv_sw_offload_cap.ip_over_vxlan_supported!=0
description:
This parameter is only supported if NV_SW_OFFLOAD_CAP.ip_over_vxlan_supported is set.\;mlxconfig_desc: When set, non-standard IPoVxLAN offload is enabled for incoming UDP port specified in IP_OVER_VXLAN_PORT.


name: esw_fdb_ipv4_ttl_modify_enable
tlv_name: nv_sw_offload_conf
offset: 0x0.6
size: 0x0.1
type: BOOL
mlxconfig_name: ESWITCH_IPV4_TTL_MODIFY_ENABLE
dependency: $nv_sw_offload_cap.esw_fdb_ipv4_ttl_modify_supported == 1
description:
When TRUE, the device will supports e-switch rules modifying TTL of packets from the uplink to a vport.


name: prio_tag_required_en
tlv_name: nv_sw_offload_conf
offset: 0x0.7
size: 0x0.1
type: BOOL
mlxconfig_name: PRIO_TAG_REQUIRED_EN
dependency: $nv_sw_offload_cap.prio_tag_required_supported == 1
description:
When set to TRUE, the system requires to always have prio tag on the network. SW of e-Switch manager should set the required flow table rules to ensure that. This field is supported only when NV_SW_OFFLOAD_CAP.prio_tag_required==1 and is reported in HCA_CAP.prio_tag_required.


name: ptp_cyc2realtime
tlv_name: nv_sw_offload_conf
offset: 0x0.10
size: 0x0.1
type: BOOL
mlxconfig_name: REAL_TIME_CLOCK_ENABLE
dependency: $nv_sw_offload_cap.ptp_cyc2realtime_supported == 1
description:
When enabled, real time clock is enabled on the device, allowing timestamps presented in real time instead of cycles.


name: pci_atomic_mode
tlv_name: nv_sw_offload_conf
offset: 0x0.12
size: 0x0.3
type: ENUM
mlxconfig_name: PCI_ATOMIC_MODE
dependency: ignore_dependency
description:
PCI Atomic mode.\;0x0: PCI_ATOMIC_DISABLED_EXT_ATOMIC_ENABLED\;0x1: PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_SERIALIZED - Atomic serialization will guarantee atomicity for multiple accesses to the same address\;0x2: PCI_ATOMICS_ENABLED_EXT_ATOMICS_DISABLED\;0x3: PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_NONCOHERENT \;0x4: PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED

textual_values:
PCI_ATOMIC_DISABLED_EXT_ATOMIC_ENABLED=0x0,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_SERIALIZED=0x1,PCI_ATOMICS_ENABLED_EXT_ATOMICS_DISABLED=0x2,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_NONCOHERENT=0x3,PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED=0x4


name: ip_over_vxlan_port
tlv_name: nv_sw_offload_conf
offset: 0x0.16
size: 0x0.16
type: UNSIGNED
mlxconfig_name: IP_OVER_VXLAN_PORT
dependency: ($nv_sw_offload_cap.ip_over_vxlan_supported!=0)&&($nv_sw_offload_conf.ip_over_vxlan_en!=0)
description:
This parameter is only supported if NV_SW_OFFLOAD_CAP.ip_over_vxlan_supported is set.\;mlxconfig_desc: The UDP port for incoming IPoVxLAN traffic (non-standard).\;minval:1


name: lro_log_timeout0
tlv_name: nv_sw_offload_conf
offset: 0x4.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT0
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #0, in microseconds. Driver can select one of the 4 configured LRO timeouts on a per Qp basis in run-time (lro_timeout_period_usecs field of the TIR context)


name: lro_log_timeout1
tlv_name: nv_sw_offload_conf
offset: 0x4.4
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT1
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #1, in microseconds. Driver can select one of the 4 configured LRO timeouts on a per Qp basis in run-time (lro_timeout_period_usecs field of the TIR context)


name: lro_log_timeout2
tlv_name: nv_sw_offload_conf
offset: 0x4.8
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT2
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #2, in microseconds. Driver can select one of the 4 configured LRO timeouts on a per Qp basis in run-time (lro_timeout_period_usecs field of the TIR context)


name: lro_log_timeout3
tlv_name: nv_sw_offload_conf
offset: 0x4.12
size: 0x0.4
type: UNSIGNED
mlxconfig_name: LRO_LOG_TIMEOUT3
dependency: ignore_dependency
description:
Log2 of Large Receive Offload (LRO) timeout #3, in microseconds. Driver can select one of the 4 configured LRO timeouts on a per Qp basis in run-time (lro_timeout_period_usecs field of the TIR context)


name: log_tx_psn_win
tlv_name: nv_sw_offload_conf
offset: 0x4.16
size: 0x0.6
type: UNSIGNED
mlxconfig_name: LOG_TX_PSN_WINDOW
dependency: $nv_sw_offload_cap.tx_psn_win_supported == 1
min_val: 0
max_val: 63
description:
Log2 of the transmission PSN window for QPs with Connected Transport Service (RC, DC, XRC).\;Value 0x0 indicates device defaults\;Value 0x3F indicates device maximal supported value\;Values exceeding the device capabilities will be considered as the device maximal supported value as well.


name: vf_migration
tlv_name: nv_sw_offload_conf
offset: 0x4.22
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MIGRATION_DISABLED=0x1,MIGRATION_ENABLED=0x2
mlxconfig_name: VF_MIGRATION_MODE
dependency: $nv_sw_offload_cap.vf_migration_supported == 1
min_val: 0
max_val: 2
description:
Defines support for VF migration\;0x0: DEVICE_DEFAULT\;0x1: MIGRATION_DISABLED\;0x2: MIGRATION_ENABLED\;Other values are reserved


name: log_max_outstanding_wqe
tlv_name: nv_sw_offload_conf
offset: 0x4.24
size: 0x0.5
type: UNSIGNED
mlxconfig_name: LOG_MAX_OUTSTANDING_WQE
dependency: $nv_sw_offload_cap.max_outstanding_wqe_supported == 1
min_val: 0
max_val: 31
description:
Log2 of the maximal amount of outstanding (uncompleted) WQEs a single Transmit Work Queue may hold. Additional WQEs will be delayed until some of the outstanding WQEs are completed.\;Value 0x0 indicates device default.\;Value 0x1F indicates device maximal supported value


name: tunnel_udp_entropy_proto_disable
tlv_name: nv_sw_offload_conf
offset: 0x4.31
size: 0x0.1
type: BOOL
mlxconfig_name: TUNNEL_IP_PROTO_ENTROPY_DISABLE
dependency: $nv_sw_offload_cap.tunnel_udp_entropy_proto_supported == 1
description:
When TRUE, tunnel encapsulation offload will exclude IP.protocol from the UDP source port entropy calculation.\;


name: vf_migration_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.14
size: 0x0.1
type: BOOL
description:
When TRUE, NV_SW_OFFLOAD_CONFIG.vf_migration supports both MIGRATION_DISABLED and MIGRATION_ENABLED modes


name: max_outstanding_wqe_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.20
size: 0x0.1
type: BOOL
description:
When TRUE, the maximal number of outstanding WQEs for a single Transmit Work Queue can be configured using in NV_SW_OFFLOAD_CONFIG


name: esw_fdb_ipv4_ttl_modify_supported
tlv_name: nv_sw_offload_cap
offset: 0x0.23
size: 0x0.1
type: BOOL
description:
When set to TRUE, the device supports enabling e-switch rules that modify TTL of packets from the uplink to a vport, using ESWITCH_IPV4_TTL_MODIFY_ENABLE.


name: pci_atomics_enabled_ext_atomics_enabled_serialized
tlv_name: nv_sw_offload_cap
offset: 0x0.25
size: 0x0.1
type: BOOL
description:
When set, NV_HCA_CONF.pci_atomic_mode supports PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_SERIALIZED mode.


name: pci_atomics_enabled_ext_atomics_enabled_nocoherent
tlv_name: nv_sw_offload_cap
offset: 0x0.27
size: 0x0.1
type: BOOL
description:
When set, NV_HCA_CONF.pci_atomic_mode supports \;PCI_ATOMICS_ENABLED_EXT_ATOMICS_ENABLED_NONCOHERENT mode.


name: disable_override
tlv_name: nv_file_id_mlnx
offset: 0x0.28
size: 0x0.1
type: BOOL
description:
When TRUE, if any existing TLV will be deleted or updated by this file, the whole upload process shall fail and no TLV shall be updated. Can only be TRUE erase_lower_priority is FLASE and keep_same_priority is TRUE


name: keep_same_priority
tlv_name: nv_file_id_mlnx
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When TRUE, installation of the file will not erase existing TLVs that are at the same priority unless they are specified in the current file.


name: per_tlv_priority
tlv_name: nv_file_id_mlnx
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When TRUE, the priority of each individual TLV in this file will be kept when writing them to the device. When FALSE, the priority of all TLVs will be the same as the priority of this NVCONFIG.


name: erase_lower_priority
tlv_name: nv_file_id_mlnx
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, installation of the file will erase all NVCONFIG parameters that are at lower priority. If the file priority is MLNX, installation of the file will not copy any TLVs from the current NVDAT partition. If the file priority is VENDOR_NVCONF, the installation of the file will only copy MLNX level TLVs.


name: year
tlv_name: nv_file_id_mlnx
offset: 0x8.16
size: 0x0.16
type: BINARY
description:
year - 4 packed BCD. Note: If year is zero, FW may copy the signature time to this TLV before copying it to flash, so the NVCONFIG component will have a date&time property.


name: year
tlv_name: nv_file_id_vendor
offset: 0x8.16
size: 0x0.16
type: BINARY
description:
year - 4 packed BCD. Note: If year is zero, FW may copy the signature time to this TLV before copying it to flash , so the NVCONFIG component will have a date&time property.


name: image_bank
tlv_name: nv_fpga_data
offset: 0x0.30
size: 0x0.2
type: UNSIGNED
description:
Select which FPGA Image to load. \;0x0: FACTORY_IMAGE - Factory-default Image\;0x1: USER_IMAGE_1 - User configured Image #1\;Other - Reserved\;


name: user_cc_en
tlv_name: nv_prog_cc
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: USER_PROGRAMMABLE_CC
dependency: ($nv_global_roce_cc_conf.legacy_cc_dcqcn==0)
description:
When set to TRUE, loading user programmed CC image is enabled. When FALSE, such image cannot be loaded. If an image already exists when this configuration is changed, the image is ignored. Valid only if ROCE_CC_LEGACY_DCQCN is FALSE.\;


name: bus0_speed_max
tlv_name: nv_global_pci_cap_3
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: PCI_GEN_1=0x0,PCI_GEN_2=0x1,PCI_GEN_3=0x2,PCI_GEN_4=0x3,PCI_GEN_5=0x4
description:
Maximal supported PCI speed width for restriction\;0x0: PCI_GEN_1\;0x1: PCI_GEN_2\;0x2: PCI_GEN_3\;0x3: PCI_GEN_4\;0x4: PCI_GEN_5


name: bus0_width_max
tlv_name: nv_global_pci_cap_3
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: PCI_X1=0x0,PCI_X2=0x1,PCI_X4=0x2,PCI_X8=0x3,PCI_X16=0x4
description:
Maximal supported PCI bus width for restriction\;0x0: PCI_X1\;0x1: PCI_X2\;0x2: PCI_X4\;0x3: PCI_X8\;0x4: PCI_X16


name: bus0_restrict_en
tlv_name: nv_global_pci_cap_3
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When TRUE, PCI bus width, speed and ASPM can be restricted according to PCI_BUS_RESTRICT_WIDTH, PCI_BUS_RESTRICT_SPEED, PCI_BUS_RESTRICT_ASPM respectively


name: pcc_handle_resource
tlv_name: nv_pcc_int
offset: 0x0.12
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,DISABLED=0x1,LOW=0x2,MEDIUM=0x3,HIGH=0x4
mlxconfig_name: PCC_HANDLE_CORE_UTIL
dependency: ($nv_pcc_int_cap.pcc_handle_resource_supported==1)
description:
Defines PCC handling core utilization\;0x0: DEVICE_DEFAULT\;0x1: DISABLED - no allocated cores, PCC disabled\;0x2: LOW - low core utilization\;0x3: MEDIUM - medium core utilization\;0x4: HIGH - high core utilization\;other values are reserved


name: np_rtt_int_data_mode
tlv_name: nv_pcc_int
offset: 0x0.24
size: 0x0.7
type: ENUM
textual_values: HPCC_LAST_HOP=0x0,HPCC_MOST_CONGESTED=0x10,NV_INT_0=0x20,RTT_V0=0x40,NO_DATA=0x48,INGRESS_BYTE=0x49
mlxconfig_name: PCC_INT_NP_RTT_DATA_MODE
description:
Defines how Notification Point (NP) generates the data for the RTT response, out of the telemetry (INT) information.\;0x00: HPCC_LAST_HOP - Use the last telemetry entry in the packet Alibaba only\;0x10: HPCC_MOST_CONGESTED - Use the telemetry entry indicating the most congested telemetry point Alibaba only\;0x20: NV_INT_0 - Nvidia Telemetry\;0x40: RTT_V0\;0x48: NO_DATA - (RTT_V1)\;0x49: INGRESS_BYTE - ingress port byte rate (RTT_v1)\;Other values are reserved

dependency:
($nv_pcc_int_cap.np_rtt_int_data_mode_last_hop==1) || ($nv_pcc_int_cap.np_rtt_int_data_mode_most_congested==1) || ($nv_pcc_int_cap.np_rtt_int_data_nv_int_0==1) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v0==1) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v1_no_data==1) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v1_ingress_byte==1)

rule:
($nv_pcc_int_cap.np_rtt_int_data_mode_last_hop==1 && $np_rtt_int_data_mode==0) || ($nv_pcc_int_cap.np_rtt_int_data_mode_most_congested==1 && $np_rtt_int_data_mode==16) || ($nv_pcc_int_cap.np_rtt_int_data_nv_int_0==1 && $np_rtt_int_data_mode==32) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v0==1 && $np_rtt_int_data_mode==64) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v1_no_data==1 && $np_rtt_int_data_mode==72) || ($nv_pcc_int_cap.np_rtt_int_data_rtt_v1_ingress_byte==1 && $np_rtt_int_data_mode==73)


name: pcc_int_en
tlv_name: nv_pcc_int
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: PCC_INT_EN
dependency: ignore_dependency
description:
When set to TRUE, the device will support PCC CC based on INT stamped RTT packets. The PCC algorithm should be programmed/configured separately to this configuration.


name: ece_disable_mask
tlv_name: nv_global_mask
offset: 0x0.0
size: 0x4.0
type: BINARY
description:
Enhanced Connection Establishment disable mask. Each bit set to 1 will cause the matching bit in ECE to be disabled in ECE negotiation.


name: steering_cache_refresh_rate
tlv_name: nv_performance_tuning_conf
offset: 0x0.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: STEERING_CACHE_REFRESH
dependency: ($nv_performance_tuning_cap.steering_cache_refresh_rate_supported==1)
description:
Log (base 2) of the period of Steering cache refreshments. Each unit represents 25us. Value 0x0 indicates device default.


name: log_hairpin_wqe_num
tlv_name: nv_performance_tuning_conf
offset: 0x0.4
size: 0x0.5
type: UNSIGNED
mlxconfig_name: HAIRPIN_LOG_WQE_NUM
description:
Log base 2 of the number of WQEs in a hairpin queues. Value 0x0 indicates device default. The implicit data per WQE is the total size (defined by SWITCH_HAIRPIN_TOT_BUFFER_SIZE) divided by the number of WQEs. This value should exceed the expected MTU.


name: multi_pci_resource_share
tlv_name: nv_performance_tuning_conf
offset: 0x0.12
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,NON_BLOCK_FAIR=0x1,NON_BLOCK_SHARED=0x2,BLOCKING_SHARED=0x3
mlxconfig_name: MULTI_PCI_RESOURCE_SHARING
description:
Defines how resources are distributed for devices configured for multi-pci interfaces (e.g. Multi-Host, Socket Direct)\;0x0: DEVICE_DEFAULT\;0x1: NON_BLOCK_FAIR - resources are fairly assigned to entities\;0x2: NON_BLOCK_SHARED - resources are partially assigned and partially shared between entities\;0x3: BLOCKING_SHARED - resources are shared between entities\;other values are reserved

dependency:
($nv_performance_tuning_cap.multi_pci_resource_share_non_block_fair == 1) || ($nv_performance_tuning_cap.multi_pci_resource_share_non_block_shared == 1) || ($nv_performance_tuning_cap.multi_pci_resource_share_blocking_shared == 1)

rule:
($multi_pci_resource_share == 0) || ($multi_pci_resource_share == 1 && $nv_performance_tuning_cap.multi_pci_resource_share_non_block_fair == 1) || ($multi_pci_resource_share == 2 && $nv_performance_tuning_cap.multi_pci_resource_share_non_block_shared == 1) || ($multi_pci_resource_share == 3 && $nv_performance_tuning_cap.multi_pci_resource_share_blocking_shared == 1)


name: icm_cache_mode
tlv_name: nv_performance_tuning_conf
offset: 0x0.16
size: 0x0.4
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,LARGE_SCALE_STEERING=0x1
mlxconfig_name: ICM_CACHE_MODE
dependency: $nv_performance_tuning_cap.icm_cache_mode_large_scale_steering == 1
description:
Tuning ICM caching mode for different setups\;0x0: DEVICE_DEFAULT\;0x1: LARGE_SCALE_STEERING - very large scale packet classification logic, with small scale for other objects\;All other values are reserved

rule:
($icm_cache_mode==0) || ($icm_cache_mode==1 && $nv_performance_tuning_cap.icm_cache_mode_large_scale_steering==1)


name: tls_optimize
tlv_name: nv_performance_tuning_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
mlxconfig_name: TLS_OPTIMIZE
dependency: $nv_performance_tuning_cap.tls_optimize_supported == 1
description:
When TRUE, the device will optimize processing for TLS operations.\;\;When FALSE, device defaults will apply for TLS processing.


name: log_sched_burst
tlv_name: nv_performance_tuning_conf
offset: 0x0.24
size: 0x0.5
type: UNSIGNED
mlxconfig_name: TX_SCHEDULER_BURST
dependency: $nv_performance_tuning_cap.sched_burst_supported == 1
min_val: 0
max_val: 31
description:
Log (base2) of the transmission scheduler default burst size, given in bytes, Value 0x0 indicates using device defaults.


name: ztt_enable
tlv_name: nv_performance_tuning_conf
offset: 0x0.31
size: 0x0.1
type: BOOL
mlxconfig_name: ZERO_TOUCH_TUNING_ENABLE
dependency: ($nv_performance_tuning_cap.ztt_supported==1)
description:
when TRUE, Zero Touch Tuning routine will automatically tune device registers in order to achieve the maximum performance


name: tls_optimize_supported
tlv_name: nv_performance_tuning_cap
offset: 0x0.29
size: 0x0.1
type: BOOL
description:
When TRUE, TLS performance optimization can be configured using NV_PERFORMANCE_TUNING_CONF.tls_optimize


name: sched_burst_supported
tlv_name: nv_performance_tuning_cap
offset: 0x0.30
size: 0x0.1
type: BOOL
description:
When TRUE, the transmit scheduler default burst size can be modified by NV_PERFORMANCE_TUNING_CONF.log_sched_burst


name: pacer_threshold_wr
tlv_name: nv_nvmf_target_conf
offset: 0x0.0
size: 0x0.5
type: UNSIGNED
mlxconfig_name: NVMF_PACER_THRESHOLD_WRITE
dependency: ($nv_nvmf_target_cap.nvmf_pacer_supported==1)
description:
Log (base 2) of IOP pacer low threshold for WRITE operations size. Smaller or equal operations will bypass the pacer. Value given in Bytes. Valid only when NVMF_PACER_MODE is PACER_ON.


name: pacer_threshold_rd
tlv_name: nv_nvmf_target_conf
offset: 0x0.8
size: 0x0.5
type: UNSIGNED
mlxconfig_name: NVMF_PACER_THRESHOLD_READ
dependency: ($nv_nvmf_target_cap.nvmf_pacer_supported==1)
description:
Log (base 2) of IOP pacer low threshold for READ operations size. Smaller or equal operations will bypass the pacer. Value given in Bytes. Valid only when NVMF_PACER_MODE is PACER_ON.


name: log_max_queue
tlv_name: nv_sw_accelerate_conf
offset: 0x0.0
size: 0x0.6
type: UNSIGNED
mlxconfig_name: LOG_MAX_QUEUE
dependency: ignore_dependency
description:
Log (base 2) of the upper limit the number of supported work queues in a single namespace (e.g. PCI function). Value 0x0 indicates using device defaults. unsupported values are saturated to the nearest supported value.


name: dbr_less_sqp
tlv_name: nv_sw_accelerate_conf
offset: 0x0.6
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ENABLE=0x1,DISABLE=0x2
mlxconfig_name: DBR_LESS_SQP
dependency: $nv_sw_offload_cap.dbr_less_sqp_supported == 1
description:
Control SQ/QP without Doorbell-Record (for send operations)\;0x0: DEVICE_DEFAULT\;0x1: ENABLE\;0x2: DISABLE\;other values are reserved


name: crypto_policy
tlv_name: nv_crypto_conf
offset: 0x0.24
size: 0x0.8
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,UNRESTRICTED=0x1,FIPS_LEVEL_2=0x2
mlxconfig_name: CRYPTO_POLICY
dependency: ignore_dependency
description:
Device cryptographic policy\;0x0: DEVICE_DEFAULT\;0x1: UNRESTRICTED\;0x2: FIPS_LEVEL_2 \;other values are reserved\;


name: flash_access
tlv_name: nv_external_host_priv_conf
offset: 0x0.16
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ENABLE=0x1,DISABLE=0x2
mlxconfig_name: HOST_PRIV_FLASH_ACCESS
description:
Defines Host privilege to perform any device flash access\;0x0: DEVICE_DEFAULT\;0x1: ENABLE\;0x2: DISABLE


name: nv_cfg_global
tlv_name: nv_external_host_priv_conf
offset: 0x0.22
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ENABLE=0x1,DISABLE=0x2
mlxconfig_name: HOST_PRIV_NV_GLOBAL
dependency: ignore_dependency
description:
Defines Host privilege to access global NV parameters.\;Note that this field has higher priority over other fields that affect global TLVs.SW should make sure other global fields in this TLV do not conflict with this one (when not DEFAULT).\;0x0: DEVICE_DEFAULT\;0x1: ENABLE\;0x2: DISABLE


name: int_cpu_conf
tlv_name: nv_external_host_priv_conf
offset: 0x0.24
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ENABLE=0x1,DISABLE=0x2
mlxconfig_name: HOST_PRIV_NV_INTERNAL_CPU
dependency: ignore_dependency
description:
Defines Host privilege to access NV_INTERNAL_CPU_CONF NV TLV\;0x0: DEVICE_DEFAULT\;0x1: ENABLE\;0x2: DISABLE


name: pcc_update
tlv_name: nv_external_host_priv_conf
offset: 0x0.26
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ENABLE=0x1,DISABLE=0x2
mlxconfig_name: HOST_PRIV_PCC_UPDATE
description:
Defines Host privilege to perform PCC algorithm update\;0x0: DEVICE_DEFAULT\;0x1: ENABLE\;0x2: DISABLE


name: max_packet_lifetime
tlv_name: nv_ib_dc_conf
offset: 0x0.8
size: 0x0.6
type: UNSIGNED
mlxconfig_name: MAX_PACKET_LIFETIME
dependency: ignore_dependency
description:
Maximum time for a packet to traverse any of the IB/RoCE paths. Time in microseconds is derived from 4.096 usec * 2^MAX_PACKET_LIFETIME.\;Value 0x0 indicates device default


name: hp_7kd_en
tlv_name: nv_enclosure_info
offset: 0x0.0
size: 0x0.1
type: BOOL
description:
When this bit is set to 1, the NIC PHY should apply PHY calibration according to the data specified in the following fields


name: current_cfg_method
tlv_name: nv_current_configurator
offset: 0x0.0
size: 0x0.8
type: ENUM
description:
Parameter from "HP ASN1 Data Structure Specification v2.8.6.asn"\;0x0: E_NONE - default config\;0x1: OS - O/S making cfg changes in the absences of any other Mgmt Util (command interface)\;0x2: E_VENDOR_SPEC - e.g. Vendor"s Option ROM, NPAR, O/S Cfg Utils (FW writes this TLV when a TLV is written from mlxconfig, that is when NVDA write for any TLV is coming from the ICMD gateway without a UEFI or flexboot "writer-ID").\;0x3: E_HP_OTHER - (when an extern-DCi-mgmt parameter with value e-None is arriving from the BMC ASN.1 API)\;0x4: E_VC_CLP - Driver or F/W detects HPE Classic C-Class SM-CLP\;0x5: E_HP_CNU - Driver or F/W detects HPE"s Converged Network Utility (when an extern-DCi-mgmt parameter with value <to-be-defined-by-HP> is arriving from the BMC ASN.1 API)\;0x6: E_HP_ONEVIEW - If manage-via-DCi value equals to HPE-OneView(6) in BaseDev-Cfg-Now is coming from the BMC ASN.1 API\;0x7: E_UEFI_HII - UEFI Option ROM executing

textual_values:
E_NONE=0x0,OS=0x1,E_VENDOR_SPEC=0x2,E_HP_OTHER=0x3,E_VC_CLP=0x4,E_HP_CNU=0x5,E_HP_ONEVIEW=0x6,E_UEFI_HII=0x7


name: time_synced
tlv_name: nv_invalidate_all_timestamp
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the time field represents the number of microseconds passed since 1/1/1970.\;Otherwise, time is the number of microseconds passed since the NIC boot (uptime)


name: ocsd_en
tlv_name: nv_rom_ocsd_ocbb
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
Enable HP on-chip temperature monitoring (OCSD) and Active Health Systems support via FW (OCBB) reporting.


name: boot_option_0
tlv_name: nv_ecpu_boot_option
offset: 0x0.0
size: 0x4.0
type: UNSIGNED
description:
Bit 0: PXE boot on port[0]\;Bit 1: PXE boot on port[1]\;Bit 2: PXE boot on port[2] \;Bit 3: PXE boot on port[3]\;Bit 4: PXE boot on OOB port\;Bit 5: PXE boot on RBT loopback\;Bit 6: Load pre-installed OS\;Bit 7: Load pre-installed grub image\;Bit 8: Remain in UEFI console\;Other bits are reserved


name: default_link_type
tlv_name: nv_vpi_link_type
offset: 0x0.2
size: 0x0.2
type: ENUM
textual_values: IB=0x1,ETH=0x2
mlxconfig_name: LINK_TYPE
dependency: ignore_dependency
description:
Select the link type (Ethernet or Infiniband) for the port\;0x1: IB - Infiniband\;0x2: ETH - Ethernet


name: roce_cc_shaper_coalescing
tlv_name: nv_roce_cc
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,DEST_IP=0x1,SOURCE_QP=0x2,_5_TUPLE=0x3
mlxconfig_name: ROCE_CC_SHAPER_COALESCE
description:
Select CC algorithm shaper coalescing for ROCE\;0x0: DEVICE_DEFAULT\;0x1: DEST_IP - shaper is selected according to dest IP\;0x2: SOURCE_QP - shaper is selected according to source QP\;0x3: _5_TUPLE - shaper is selected according to 5-tuples\;other values are reserved

dependency:
($nv_pcc_int_cap.roce_cc_shaper_coalese_dest_ip==1) || ($nv_pcc_int_cap.roce_cc_shaper_coalese_source_qp==1) || ($nv_pcc_int_cap.roce_cc_shaper_coalese_5_tuple==1)


name: ib_cc_shaper_coalescing
tlv_name: nv_roce_cc
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,REMOTE_LID=0x2
mlxconfig_name: IB_CC_SHAPER_COALESCE
dependency: ($nv_pcc_int_cap.ib_cc_shaper_coalese_remote_lid==1)
description:
Select CC algorithm shaper coalescing for IB\;0x0: DEVICE_DEFAULT\;0x2: REMOTE_LID - shaper is selected according to remote lid (IB)\;other values are reserved


name: clamp_tgt_rate_after_time_inc
tlv_name: nv_roce_cc_ecn
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: CLAMP_TGT_RATE_AFTER_TIME_INC
dependency: ignore_dependency
description:
When receiving a CNP, the target rate should be updated if the transmission rate was increased due to the timer, and not only due to the byte counter


name: rpg_threshold
tlv_name: nv_roce_cc_ecn
offset: 0xC.0
size: 0x0.5
type: UNSIGNED
mlxconfig_name: RPG_THRESHOLD
dependency: ignore_dependency
description:
The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states.


name: rpg_max_rate
tlv_name: nv_roce_cc_ecn
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
mlxconfig_name: RPG_MAX_RATE
dependency: ignore_dependency
description:
The maximum rate, in Mbits per second, at which an RP can transmit. Once this limit is reached, the RP rate limited is released and the flow is not rate limited any more (0=Full Port Speed).


name: rpg_gd
tlv_name: nv_roce_cc_ecn
offset: 0x1C.0
size: 0x0.4
type: UNSIGNED
mlxconfig_name: RPG_GD
dependency: ignore_dependency
description:
If a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval to (1-Alpha/Gd)*CurrentRate. rpg_gd is given as log2(Gd), where Gd may only be powers of 2.


name: rpg_min_dec_fac
tlv_name: nv_roce_cc_ecn
offset: 0x20.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: RPG_MIN_DEC_FAC
dependency: ignore_dependency
min_val: 1
max_val: 100
description:
The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage (1-100).


name: rate_to_set_on_first_cnp
tlv_name: nv_roce_cc_ecn
offset: 0x28.0
size: 0x0.17
type: UNSIGNED
mlxconfig_name: RATE_TO_SET_ON_FIRST_CNP
dependency: ignore_dependency
description:
The rate that is set for the flow when a rate limiter is allocated to it upon first CNP received, in Mbps (=Full Port Speed).


name: dce_tcp_g
tlv_name: nv_roce_cc_ecn
offset: 0x2C.0
size: 0x0.10
type: UNSIGNED
mlxconfig_name: DCE_TCP_G
dependency: ignore_dependency
min_val: 1
description:
Used to update the congestion estimator (alpha) once every dce_tcp_rtt microseconds, according to the equation:\;Alpha = (cnp_received * dceTcpG) + (1 - dceTcpG) * alpha .\;dceTcpG is divided by 2^10.\;cnp_received is set to one if a CNP was received for this flow during period since the previous update and the current update


name: rate_reduce_monitor_period
tlv_name: nv_roce_cc_ecn
offset: 0x34.0
size: 0x0.17
type: UNSIGNED
mlxconfig_name: RATE_REDUCE_MONITOR_PERIOD
dependency: ignore_dependency
min_val: 1
description:
The minimum time between 2 consecutive rate reductions for a single flow. Rate reduction will occur only if a CNP is received during the relevant time interval.


name: initial_alpha_value
tlv_name: nv_roce_cc_ecn
offset: 0x38.0
size: 0x0.10
type: UNSIGNED
mlxconfig_name: INITIAL_ALPHA_VALUE
dependency: ignore_dependency
description:
The initial value of alpha to use when receiving the first CNP for a flow. Expressed in a fixed point fraction of 2^10.


name: cnp_prio_mode
tlv_name: nv_roce_cc_ecn
offset: 0x40.3
size: 0x0.1
type: BOOL
mlxconfig_name: CNP_RES_PRIO_MODE
description:
If TRUE, CNP packets for this port contain priority from a received request. If FALSE, CNP responses use value set by CNP_802P_PRIO.


name: rpg_threshold
tlv_name: nv_roce_cc_qcn
offset: 0xC.0
size: 0x0.5
type: UNSIGNED
description:
The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states.\;


name: rpg_max_rate
tlv_name: nv_roce_cc_qcn
offset: 0x10.0
size: 0x4.0
type: UNSIGNED
description:
The maximum rate, in Mbits per second, at which an RP can transmit. Once this limit is reached, the RP rate limited is released and the flow stops being limited (0=Full Port Speed)\;


name: rpg_gd
tlv_name: nv_roce_cc_qcn
offset: 0x1C.0
size: 0x0.4
type: UNSIGNED
description:
When a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval to (1-Alpha/Gd)*CurrentRate. rpg_gd is given as log2(Gd), where Gd may only be powers of 2.\;


name: rpg_min_dec_fac
tlv_name: nv_roce_cc_qcn
offset: 0x20.0
size: 0x0.8
type: UNSIGNED
description:
The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage (1-100).\;


name: lldp_nb_rx_mode
tlv_name: nv_lldp_nb_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: OFF=0x0,MANDATORY=0x1,ALL=0x2
mlxconfig_name: LLDP_NB_RX_MODE
dependency: $nv_lldp_nb_cap.lldp_nb_rx_cap!=0
max_val: $nv_lldp_nb_cap.lldp_nb_rx_cap
description:
Enable the internal LLDP client, and define which TLV it will process.\;0x0: OFF - Doesnot listen to incoming LLDP BPDU (incoming LLDP frames will be routed to the host)\;0x1: MANDATORY - Listen to incoming LLDP frames, store only the mandatory LLDP BPDUs (1..3)\;0x2: ALL - Receive and store all incoming LLDP BPDUs


name: lldp_nb_tx_mode
tlv_name: nv_lldp_nb_conf
offset: 0x0.30
size: 0x0.2
type: ENUM
textual_values: OFF=0x0,MANDATORY=0x1,ALL=0x2
mlxconfig_name: LLDP_NB_TX_MODE
dependency: $nv_lldp_nb_cap.lldp_nb_tx_cap!=0
max_val: $nv_lldp_nb_cap.lldp_nb_tx_cap
description:
Select which LLDP TLV will be generated by the NIC\;0x0: OFF - NIC internal LLDP client will not send LLDP frames \;0x1: MANDATORY - Transmits only mandatory LLDP BPDU (ChassisID, PortID & TTL)\;0x2: ALL - Transmits optional LLDP BPDU if configured


name: lldp_nb_tx_buffer_size
tlv_name: nv_lldp_nb_conf
offset: 0x8.16
size: 0x0.16
type: UNSIGNED
description:
The size in bytes of   LLPD client must reserve for transmitted TLVs. The buffer size must be big enough to hold all  mandatory TLVs (chassisID, PortID & TTL) as well as all  optional TLVs that the client needs to send.


name: lldp_nb_rx_cap
tlv_name: nv_lldp_nb_cap
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: NA=0x0,MANDATORY=0x1,ALL=0x2
description:
0x0: NA - Reception and storing of LLDP frames is not supported (incoming frames will be forwarded to the host)\;0x1: MANDATORY - The client can only store received  mandatory LLDP-TLVs \;0x2: ALL - The client can receive and store incoming LLDP TLVs


name: lldp_nb_tx_cap
tlv_name: nv_lldp_nb_cap
offset: 0x0.30
size: 0x0.2
type: ENUM
textual_values: NA=0x0,MANDATORY=0x1,ALL=0x2,reserved=0x3
description:
0x0: NA - LLDP transmission not supported \;0x1: MANDATORY - The LLDP client only support sending  the mandatory LLDP NB TLVs (ChassisID, PortID & TTL)\;0x2: ALL - The LLDP client support sending mandatory and optional TLVs \;0x3: reserved


name: max_num_of_tx_optional_lldp_tlv
tlv_name: nv_lldp_nb_cap
offset: 0x8.0
size: 0x0.7
type: UNSIGNED
description:
The maximum number of optional LLDP TLVs that are supported by the firmware. The firmware is searching for LLDP NB TLV to send from type 0x110 to type (0x110 + this field)\;Default: 16


name: rtt_resp_dscp
tlv_name: nv_roce_conf
offset: 0x0.0
size: 0x0.6
type: UNSIGNED
mlxconfig_name: ROCE_RTT_RESP_DSCP
dependency: ignore_dependency
description:
The DiffServ Code Point of the generated RTT response for this port. If not set, RTT request value will be used. Overrides PCC_INT_NP_RTT_DSCP


name: rtt_resp_dscp_mode
tlv_name: nv_roce_conf
offset: 0x0.14
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,FIXED_VALUE=0x1,RTT_REQUEST=0x2
mlxconfig_name: ROCE_RTT_RESP_DSCP_MODE
dependency: ignore_dependency
description:
Defines the method for setting IP.DSCP in RTT response packets\;0x0: DEVICE_DEFAULT\;0x1: FIXED_VALUE - taken from ROCE_RTT_RESP_DSCP\;0x2: RTT_REQUEST - taken from the RTT request\;other values are reserved


name: keep_link_up_on_boot
tlv_name: nv_keep_link_up
offset: 0x0.2
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_LINK_UP_ON_BOOT
description:
When set, the NIC keeps the link up as long as the server is not in standby mode and a driver is not initialized.


name: keep_link_up_on_standby
tlv_name: nv_keep_link_up
offset: 0x0.3
size: 0x0.1
type: BOOL
mlxconfig_name: KEEP_LINK_UP_ON_STANDBY
description:
When set, the NIC keeps the link up from power-up until the server is turned on, and when the server is in standby\;mode (PCI L2/3 state). \;Note: The link will be kept up only if the server can provide enough power during standby (via PCI rails or AUX power).


name: do_not_clear_port_stats
tlv_name: nv_keep_link_up
offset: 0x0.4
size: 0x0.1
type: BOOL
mlxconfig_name: DO_NOT_CLEAR_PORT_STATS
description:
When set, the port statistic counters are not cleared on first host init. When cleared the port statistics are cleared on first host init


name: num_of_vl
tlv_name: nv_qos_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: _1_VL=0x1,_2_VLs=0x2,_4_VLs=0x3,_8_VLs=0x4,_15_VLs=0x5
mlxconfig_name: NUM_OF_VL
dependency: ignore_dependency
min_val: 1
max_val: $nv_qos_cap.max_num_of_vl
description:
Number of Infiniband Virtual Lanes for this port\;0x1: _1_VL - VL0 only\;0x2: _2_VLs - VL0, VL1\;0x3: _4_VLs - VL0..VL3\;0x4: _8_VLs - VL0..VL7\;0x5: _15_VLs --VL0, VL14 (VL15 is always present for MADs)


name: num_of_tc
tlv_name: nv_qos_conf
offset: 0x0.4
size: 0x0.4
type: ENUM
textual_values: _8_TCs=0x0,_1_TC=0x1,_2_TCs=0x2,_3_TCs=0x3,_4_TCs=0x4,_5_TCs=0x5,_6_TCs=0x6,_7_TCs=0x7
mlxconfig_name: NUM_OF_TC
dependency: ignore_dependency
min_val: ($nv_qos_cap.max_num_of_tc==0)?0:1
max_val: ($nv_qos_cap.max_num_of_tc==0)?7:$nv_qos_cap.max_num_of_tc
description:
Number of traffic classes, when DCB-X is enabled, this is the maximum number of TC that can negotiate with the remote peer. \;0x0: _8_TCs\;0x1: _1_TC\;0x2: _2_TCs\;0x3: _3_TCs\;0x4: _4_TCs\;0x5: _5_TCs\;0x6: _6_TCs\;0x7: _7_TCs


name: num_of_pfc
tlv_name: nv_qos_conf
offset: 0x0.8
size: 0x0.4
type: UNSIGNED
mlxconfig_name: NUM_OF_PFC
dependency: ignore_dependency
max_val: $nv_qos_cap.max_num_pfc
description:
Number of IEEE priorities that may simultaneously support flow control. \; (See pfc_cap_admin DCBX_PARAM Register)


name: log_vl15_buffer_size
tlv_name: nv_qos_conf
offset: 0x0.12
size: 0x0.4
type: UNSIGNED
mlxconfig_name: VL15_BUFFER_SIZE
dependency: $nv_qos_cap.log_max_vl15_buffer_size!=0
max_val: $nv_qos_cap.log_max_vl15_buffer_size
description:
Log (base 2) of the VL15 receive port buffer, given in units of 512B. Value 0x0 indicates device defaults.\;Valid only for Infiniband links.


name: qos_trust_state
tlv_name: nv_qos_conf
offset: 0x0.16
size: 0x0.3
type: ENUM
textual_values: TRUST_PORT=0x0,TRUST_PCP=0x1,TRUST_DSCP=0x2,TRUST_DSCP_PCP=0x3
mlxconfig_name: QOS_TRUST_STATE
dependency: $nv_qos_cap.qos_trust_state_supported!=0
valid_bit: qos_trust_state_en
description:
Identifies the layer trusted to carry QoS/Flow Control information\;0x0: TRUST_PORT - use transmit port\;0x1: TRUST_PCP - use VLAN.PCP field\;0x2: TRUST_DSCP - use IP.DSCP field\;0x3: TRUST_DSCP_PCP - use VLAN.PCP when IP.DSCP is not present


name: max_num_of_vl
tlv_name: nv_qos_cap
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: _1_VL=0x1,_2_VLs=0x2,_4_VLs=0x3,_8_VLs=0x4,_15_VLs=0x5
description:
Maximum number of VLs supported by the HBA.\;0x1: _1_VL - VL0 only\;0x2: _2_VLs - VL0, VL1\;0x3: _4_VLs - VL0..VL3\;0x4: _8_VLs - VL0..VL7\;0x5: _15_VLs -- VL0..VL14 (VL15 is always present for MADs)


name: log_max_vl15_buffer_size
tlv_name: nv_qos_cap
offset: 0x0.12
size: 0x0.4
type: UNSIGNED
description:
Maximum value supported for NV_QOS_CONF.log_vl15_buffer_size. Value 0x0 indicates NV_QOS_CONF.log_vl15_buffer_size is not supported.


name: qos_trust_state_supported
tlv_name: nv_qos_cap
offset: 0x0.16
size: 0x0.4
type: UNSIGNED
description:
Bitmask indicating which modes are supported for VN_QOS_CONF.qos_trust_state\;bit 0: TRUST_PORT\;bit 1: TRUST_PCP\;bit 2: TRUST_DSCP\;bit 3: TRUST_DSCP_PCP


name: duplicated_mac_action_mode
tlv_name: nv_mpfs_conf
offset: 0x0.0
size: 0x0.4
type: ENUM
textual_values: LAST_CFG=0x0,LOAD_BALANCE=0x1
mlxconfig_name: DUP_MAC_ACTION
dependency: ignore_dependency
description:
Defines the forwarding behavior in MPFS for MACs which are duplicated in more than one PF.\;0x0: LAST_CFG - last PF which added the MAC will receive the traffic.\;0x1: LOAD_BALANCE - MPFS will load-balance ipv4 traffic for packets with destination MAC addresses that belong to more than one PF between all PFs that have this MAC


name: loopback_disable_mc
tlv_name: nv_mpfs_conf
offset: 0x0.5
size: 0x0.1
type: BOOL
mlxconfig_name: MPFS_MC_LOOPBACK_DISABLE
dependency: $nv_mpfs_cap.loopback_disable_supported!=0
description:
When TRUE, MC traffic from PFs/Hosts will be sent to uplink and not duplicated to any of the other PFs/Hosts


name: unknown_uplink_mac_flood
tlv_name: nv_mpfs_conf
offset: 0x0.7
size: 0x0.1
type: BOOL
mlxconfig_name: UNKNOWN_UPLINK_MAC_FLOOD
dependency: $nv_mpfs_cap.unknown_uplink_mac_flood_supported!=0
description:
Defines the forwarding behavior in MPFS for packets arriving from the network (uplink) with destination MAC address that does not appear in the MPFS FDB.\;When TRUE, these packets are flooded to all local MPFS\;ports.\;When FALSE, these packets are dropped.


name: ib_routing_mode
tlv_name: nv_mpfs_conf
offset: 0x0.31
size: 0x0.1
type: ENUM
textual_values: GID=0x0,LID=0x1
mlxconfig_name: IB_ROUTING_MODE
dependency: $nv_mpfs_cap.ib_routing_mode_supported!=0
description:
Select the routing mode for Infiniband among the PFs (and hosts, if applicable)\;0x0: GID - each PF has a unique GID\;0x1: LID - each PF has a unique LID


name: phy_auto_neg_mode
tlv_name: nv_link_phy_conf
offset: 0x0.24
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,AUTO_NEG_ENABLED=0x1,AUTO_NEG_DISABLED=0x2
mlxconfig_name: PHY_AUTO_NEG
dependency: ($nv_link_phy_cap.phy_auto_neg_mode_supported==1)
description:
Control link Auto Negotiation operation\;0x0: DEVICE_DEFAULT\;0x1: AUTO_NEG_ENABLED\;0x2: AUTO_NEG_DISABLED\;other values are reserved.


name: phy_fec_override
tlv_name: nv_link_phy_conf
offset: 0x0.28
size: 0x0.3
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MODE_1=0x1,MODE_2=0x2,MODE_3=0x3,MODE_4=0x4
mlxconfig_name: PHY_FEC_OVERRIDE
dependency: ($nv_link_phy_cap.phy_fec_override_supported==1)
description:
Customizes FEC configuration of the port\;0x0: DEVICE_DEFAULT\;0x1: MODE_1 - disabled DME, disabled FEC for 25G/50G/100G\;0x2: MODE_2 - disabled DME, RS FEC for 25G/50G/100G\;0x3: MODE_3 - disabled DME, FC FEC for 25G/50G or RS FEC for 100G\;0x4: MODE_4 - disable non_dme (enable Auto Negotiation)\;Other values are reserved


name: phy_rate_mask
tlv_name: nv_link_phy_conf
offset: 0x4.0
size: 0x4.0
type: UNSIGNED
mlxconfig_name: PHY_RATE_MASK
dependency: ($nv_link_phy_conf.phy_rate_mask_override==1)
description:
Enables the supported rates for the link. Each bit represents a rate, set bit indicates the speed may be used, if supported by the device,\;Valid when PHY_RATE_MASK_OVERRIDE is TRUE.\;\;Bit 0 - SGMII_100M\;Bit 1 - 1000BASE-X / SGMII\;Bit 3 - 5GBASE-R\;Bit 4 - XFI / XAUI-1 - 10G\;Bit 5 - XLAUI-4/XLPPI-4 - 40G\;Bit 6 - 25GAUI-1/ 25GBASE-CR / KR\;Bit 7 - 50GAUI-2 / LAUI-2/ 50GBASE-CR2/KR2\;Bit 8 - 50GAUI-1 /50GBASE-CR / KR\;Bit 9 - CAUI-4 / 100GBASE-CR4 / KR4\;Bit 10 - 100GAUI-2 / 100GBASE-CR2 / KR2\;Bit 11 - 100GAUI-1 / 100GBASE-CR / KR\;Bit 12 - 200GAUI-4 / 200GBASE-CR4/KR4\;Bit 13 - 200GAUI-2 / 200GBASE-CR2/KR2\;Bit 15 - 400GAUI-8/ 400GBASE-CR8\;Bit 16 - 400GAUI-4/ 400GBASE-CR4\;Bit 19 - 800GAUI-8/ 800GBASE-CR8\;Bit 31 - SGMII_10M\;


name: en_wol_magic
tlv_name: nv_wol_cap
offset: 0x0.10
size: 0x0.1
type: BOOL
description:
This bit is set when Wake-On-Lan magic packet is supported for this host and port. Note that WOL support mandates a special circuitry on the NIC.


name: total_sf
tlv_name: nv_pf_pci_conf
offset: 0x0.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: PF_TOTAL_SF
dependency: $nv_global_pci_cap.per_pf_num_sf_supported==1
valid_bit: pf_total_sf_en
description:
The total number of Sub Function partitions (SFs) that can be sup\;ported, for this PF. \;Valid only when PER_PF_NUM_SF is set to TRUE


name: log_sf_bar_size
tlv_name: nv_pf_pci_conf
offset: 0x0.24
size: 0x0.8
type: UNSIGNED
mlxconfig_name: PF_SF_BAR_SIZE
dependency: $nv_global_pci_cap.per_pf_num_sf_supported==1
valid_bit: pf_total_sf_en
description:
Log (base 2) of the BAR size of a single SF, given in KB. Valid only when PF_TOTAL_SF is non-zero and PER_PF_NUM_SF is set to TRUE.


name: num_pf_msix
tlv_name: nv_pf_pci_conf
offset: 0x4.0
size: 0x0.12
type: UNSIGNED
mlxconfig_name: PF_NUM_PF_MSIX
dependency: $nv_global_pci_cap.per_pf_num_msix_supported == 1
description:
Number of MSI-X vectors assigned for this PF\;Value 0x0 indicates device defaults.\;Valid only when PF_NUM_PF_MSIX_VALID is set to TRUE


name: num_vf_msix
tlv_name: nv_pf_pci_conf
offset: 0x4.12
size: 0x0.12
type: UNSIGNED
mlxconfig_name: PF_NUM_VF_MSIX
description:
Number of MSI-X vectors assigned for each VF associated with the PF.\;Value 0x0 indicates device defaults\;valid only when PER_PF_NUM_VF_MSIX is set to TRUE.


name: total_vf
tlv_name: nv_pf_pci_conf
offset: 0x8.0
size: 0x0.16
type: UNSIGNED
mlxconfig_name: PF_NUM_OF_VF
dependency: ($nv_global_pci_cap.per_pf_total_vf_supported == 1 && $nv_global_pci_conf.per_pf_total_vf == 1)
valid_bit: pf_total_vf_en
description:
The total number of Virtual Functions (VFs) that will be exposed, for this PF. Value 0x0 indicates SR-IOV will be disabled.\;Valid only when PF_NUM_OF_VF_VALID is set to TRUE


name: virtual_guid_en
tlv_name: nv_virt_guid_addr
offset: 0x0.31
size: 0x0.1
type: BOOL
description:
When set, the PF will use the address defined in the "virtual_node_guid" instead of the original MAC.


name: silent_mode
tlv_name: nv_hca_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
mlxconfig_name: SILENT_MODE
dependency: $nv_hca_cap.silent_mode_supported!=0
description:
When TRUE, the networking function is disconnected from the network. It cannot transmit/received traffic directly to/from the network. Any communication must be done within the function, or by directing the traffic through another function.


name: mkey_by_name_reserve_mode
tlv_name: nv_hca_conf
offset: 0x0.24
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MKEY_RANGE_DISABLE=0x1,MKEY_RANGE_ENABLE=0x2
mlxconfig_name: MKEY_BY_NAME_RANGE
dependency: $nv_hca_cap.mkey_by_name_reserve_supported!=0
description:
Control support for reserved Mkey range for Mkeys created by name. See MKEY_BY_NAME.\;0x0: DEVICE_DEFAULT\;0x1: MKEY_RANGE_DISABLE\;0x2: MKEY_RANGE_ENABLE\;other values are reserved


name: roce_ctrl
tlv_name: nv_hca_conf
offset: 0x0.26
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,ROCE_DISABLE=0x1,ROCE_ENABLE=0x2
mlxconfig_name: ROCE_CONTROL
dependency: $nv_hca_cap.roce_ctrl_supported!=0
description:
Control support for RDMA over Converged Ethernet (RoCE)\;0x0: DEVICE_DEFAULT\;0x1: ROCE_DISABLE\;0x2: ROCE_ENABLE\;other values are reserved


name: pci_data_wr_ordering_mode
tlv_name: nv_hca_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: per_mkey=0x0,force_relax=0x1
mlxconfig_name: PCI_WR_ORDERING
dependency: $nv_hca_cap.pci_data_wr_ordering_supported!=0
description:
Controls the PCI ordering attribute for write accesses from the device\;0x0: per_mkey - Each MKey may be configured differently for Relaxed Ordering\;0x1: force_relax - All MKeys will be set to use Relaxed Ordering at creation time\;show this setting only when NV_PCI_CONF. advanced_pci_settings is true.


name: esw_manager
tlv_name: nv_ecpf_conf
offset: 0x0.0
size: 0x0.2
type: ENUM
textual_values: EXTERNAL_HOST_PF=0x0,ECPF=0x1
mlxconfig_name: ECPF_ESWITCH_MANAGER
description:
This parameter is deprecated for INTERNAL_CPU_ESWITCH_MANAGER\;\;Select who owns the E-switch.\;0x0: EXTERNAL_HOST_PF\;0x1: ECPF\;

dependency:
($nv_ecpf_cap.esw_manager_ecpf_supported==1) || ($nv_ecpf_cap.esw_manager_external_host_pf_supported==1)

rule:
($esw_manager==0 && $nv_ecpf_cap.esw_manager_external_host_pf_supported==1) || ($esw_manager==1 && $nv_ecpf_cap.esw_manager_ecpf_supported==1)


name: page_supplier
tlv_name: nv_ecpf_conf
offset: 0x0.8
size: 0x0.2
type: ENUM
textual_values: EXTERNAL_HOST_PF=0x0,ECPF=0x1
mlxconfig_name: ECPF_PAGE_SUPPLIER
description:
This parameter is deprecated for INTERNAL_CPU_PAGE_SUPPLIER\;\;Select who supplies ICM pages of the external host functions to device. \;0x0: EXTERNAL_HOST_PF - External host supplies required ICM pages to handle it.\;0x1: ECPF - ECPF supplies required ICM pages to handle the external host.\;

dependency:
($nv_ecpf_cap.external_host_page_supplier_ecpf_supported==1) || ($nv_ecpf_cap.external_host_page_supplier_external_host_pf_supported==1)

rule:
($page_supplier==0 && $nv_ecpf_cap.external_host_page_supplier_external_host_pf_supported==1) || ($page_supplier==1 && $nv_ecpf_cap.external_host_page_supplier_ecpf_supported==1)


name: reneg_on_change
tlv_name: nv_external_port_ctrl
offset: 0x0.2
size: 0x0.1
type: BOOL
mlxconfig_name: RENEG_ON_CHANGE
description:
When cleared, a link-down/up sequence from the driver (PAOS) triggers re-negotiation of the link speed and parameters with the remote peer. When set, a link down/up sequence will trigger re-negotiation only if any link parameters were changed by a driver since last link negotiation. \;This parameter is applicable when the port_owner parameter is set for this PF


name: force_link_down
tlv_name: nv_external_port_ctrl
offset: 0x0.4
size: 0x0.1
type: BOOL
description:
When TRUE, link down requests will cause the link to shut down regardless of other considerations. Valid only if PORT_OWNER is set.


name: boot_ip_ver
tlv_name: nv_rom_boot_conf2
offset: 0x0.8
size: 0x0.2
type: ENUM
textual_values: IPv4=0x0,IPv6=0x1,IPv4_IPv6=0x2,IPv6_IPv4=0x3
mlxconfig_name: IP_VER
dependency: $nv_rom_cap.boot_ip_ver!=0
description:
Select which IP protocol version will be used by Flexboot. If both are configured, Flexboot will try to boot with the 2nd protocol only if DHCP parameters for the first protocol are not available, or if booting with the first protocol has failed.\;0x0: IPv4\;0x1: IPv6\;0x2: IPv4_IPv6\;0x3: IPv6_IPv4\;


name: undi_network_wait
tlv_name: nv_rom_boot_conf2
offset: 0x0.16
size: 0x0.8
type: UNSIGNED
mlxconfig_name: BOOT_UNDI_NETWORK_WAIT
dependency: ignore_dependency
description:
The number of seconds Flexboot waits after issuing a UNDI open commands until it starts using the interface.


name: stp
tlv_name: nv_rom_debug_level
offset: 0x4.0
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_STP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Spanning Tree Protocol\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: romprefix
tlv_name: nv_rom_debug_level
offset: 0x4.2
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_ROMPREFIX
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's driver bootstrap code\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: arp
tlv_name: nv_rom_debug_level
offset: 0x4.8
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_ARP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Address resolution Protocol (ARP)\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: neighbor
tlv_name: nv_rom_debug_level
offset: 0x4.10
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NEIGHBOR
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot's Neighbor table (which is filled by ARP and NDP)\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: ndp
tlv_name: nv_rom_debug_level
offset: 0x4.12
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDP
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s IPv6 Neighbor Discovery Protocol\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: driver
tlv_name: nv_rom_debug_level
offset: 0x4.16
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_DRV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s driver (init, teardown, poll CQ etc) \;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic
tlv_name: nv_rom_debug_level
offset: 0x4.18
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC driver (init, teardown, poll CQ etc) \;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_cmd
tlv_name: nv_rom_debug_level
offset: 0x4.20
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_CMD
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver interface\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_device
tlv_name: nv_rom_debug_level
offset: 0x4.22
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_DEV
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver tear-down and bring ups operations.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: nodnic_port
tlv_name: nv_rom_debug_level
offset: 0x4.24
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_NDRV_PORT
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for Flexboot"s NODNIC Driver port management.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: driver_settings
tlv_name: nv_rom_debug_level
offset: 0x8.8
size: 0x0.2
type: ENUM
textual_values: DISABLE=0x0,BASIC=0x1,ADVANCED=0x2,ALL=0x3
mlxconfig_name: BOOT_DBG_LOG_DRIVER_SETTINGS
dependency: ($nv_rom_cap.flexboot_debug_en==1)&&($nv_rom_debug_level.debug_log_en==1)
description:
Debug level for non volatile configuration management.\;0x0: DISABLE\;0x1: BASIC\;0x2: ADVANCED\;0x3: ALL\;


name: panic_banner
tlv_name: nv_rom_flexboot_debug
offset: 0x0.29
size: 0x0.2
type: ENUM
textual_values: PRINT=0x0,HALT=0x1,OPEN_SHELL=0x2
description:
Flexboot behavior on critical failure \;0x0: PRINT - print error to screen\;0x1: HALT - freeze system\;0x2: OPEN_SHELL - open ipxe shell


name: uefi_log_severity
tlv_name: nv_rom_uefi_debug_level
offset: 0x0.24
size: 0x0.2
type: ENUM
textual_values: ERROR=0x0,WARNING=0x1,INFO=0x2,DEBUG=0x3
mlxconfig_name: UEFI_LOG_MIN_SEVERITY
dependency: ($nv_rom_uefi_debug_level.uefi_logs!=0)&&($nv_rom_cap.uefi_logs_en==1)
description:
NIC/HBA UEFI expansion ROM\;0x0: ERROR\;0x1: WARNING\;0x2: INFO\;0x3: DEBUG\;Note - Enabling of debug logs for specific modules is possible after setting the severity to DEBUG.\;


name: uefi_logs
tlv_name: nv_rom_uefi_debug_level
offset: 0x0.28
size: 0x0.4
type: ENUM
textual_values: DISABLED=0x0,STDOUT=0x1,STDERR=0x2
mlxconfig_name: UEFI_LOGS
dependency: ($nv_rom_cap.uefi_logs_en==1)
description:
Select the output device logs generated by the NIC/HBA\;UEFI expansion ROM.\;0x0: DISABLED\;0x1: STDOUT\;0x2: STDERR\;


name: flexboot_banner_timeout
tlv_name: nv_rom_banner_timeout
offset: 0x0.0
size: 0x0.4
type: UNSIGNED
description:
Number of seconds to wait when displaying the timer for the boot menu key-press. If set to 0 the boot menu is disabled. The boot menu is only allowed to write values between 1 and 15. UEFI and mlxconfig may write 0.


name: legacy_boot_protocol
tlv_name: nv_rom_boot_conf1
offset: 0x0.16
size: 0x0.8
type: ENUM
textual_values: NONE=0x0,PXE=0x1,ISCSI=0x2,PXE_WO_FAIL_ISCSI=0x4,ISCSI_WO_FAIL_PXE=0x5
mlxconfig_name: LEGACY_BOOT_PROTOCOL
dependency: ignore_dependency
description:
Select boot protocol for legacy BIOS expansion ROM (Flexboot)\;0x0: NONE - The expansion ROM will not add this PCI PF as a boot target during the POST stage.\;0x1: PXE - The expansion ROM will use PXE boot.\;0x2: ISCSI - The expansion ROM will use iSCSI boot.\;0x4: PXE_WO_FAIL_ISCSI - PXE without fail-over to ISCSI. Supported when legacy_boot_wo_failover_supported==1.\;0x5: ISCSI_WO_FAIL_PXE - ISCSI without fail-over to PXE.Supported when legacy_boot_wo_failover_supported==1.


name: boot_retry_count
tlv_name: nv_rom_boot_conf1
offset: 0x0.24
size: 0x0.3
type: ENUM
textual_values: NONE=0x0,_1=0x1,_2=0x2,_3=0x3,_4=0x4,_5=0x5,_6=0x6,UNLIMITED=0x7
mlxconfig_name: BOOT_RETRY_CNT1
description:
Number of retries to attempt in case of boot failure (FlexBoot)\;0x0: NONE\;0x1: _1\;0x2: _2\;0x3: _3\;0x4: _4\;0x5: _5\;0x6: _6\;0x7: UNLIMITED\;


name: boot_legacy_interrupt_disable
tlv_name: nv_rom_boot_conf1
offset: 0x0.27
size: 0x0.1
type: BOOL
mlxconfig_name: BOOT_INTERRUPT_DIS
dependency: $nv_rom_cap.boot_legacy_interrupt_disable_supported!=0
description:
When set to TRUE, legacy interrupts should not be used for receive/transmit indication. Polling should be used instead.\;Supported only if boot_legacy_interrupt_disable_supported =TRUE.


name: lacp_dis
tlv_name: nv_rom_boot_conf1
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: BOOT_LACP_DIS
dependency: $nv_rom_cap.lacp_config_en!=0
description:
Disable IEEE 802.3ad Link Aggregation Control Protocol (LACP) for legacy BIOS expansion ROM (Flexboot).\;


name: client_identifier
tlv_name: nv_rom_ib_dhcp_conf
offset: 0x0.24
size: 0x0.4
type: ENUM
textual_values: ROM_DEFAULT=0x0,NO_CLIENT_IDENTIFIER=0x1,SEND_CLIENT_IDENTIFIER=0x2
description:
Select if the expansion ROM should add a Client Identifier to DHCP DISCOVER and REQUEST packets over InfiniBand.\;0x0: ROM_DEFAULT \;0x1: NO_CLIENT_IDENTIFIER\;0x2: SEND_CLIENT_IDENTIFIER\;When set, the UEFI driver modifies the DHCP packet sent by the upper layers.


name: boot_to_target
tlv_name: nv_rom_iscsi_general_conf
offset: 0x0.22
size: 0x0.2
type: ENUM
textual_values: ENABLED=0x0,DISABLED=0x1,ONE_TIME_DISABLED=0x2
description:
Boot to iSCSI target after connection\;0x0: ENABLED - Boot from target\;0x1: DISABLED - Don"t boot from target (target will be hooked if configured and iscsi_keep_san_dev_en is set)\;0x2: ONE_TIME_DISABLED - Used for installing a new OS on the ISCSI target. Flexboot will not boot from the target once (e.g. DISABLED), and then will automatically change the value to ENABLED.


name: lun_busy_retry_count
tlv_name: nv_rom_iscsi_general_conf
offset: 0x8.0
size: 0x0.8
type: UNSIGNED
description:
Number of connection attempts to make if the iSCSI target is busy. Valid values are between 0 and 60.


name: iscsi_drive_num
tlv_name: nv_rom_iscsi_general_conf
offset: 0x8.16
size: 0x0.8
type: ENUM
textual_values: HDD1=0x80,HDD2=0x81,HDD3=0x82,HDD4=0x83
description:
The HDD number for the hooked iSCSI target in legacy BIOS int13 drive table.\;0x80: HDD1\;0x81: HDD2\;0x82: HDD3\;0x83: HDD4


name: value
tlv_name: nv_rom_iscsi_initiator_name
offset: 0x0.24
size: 0xe0.0
type: STRING
description:
This configuration sets the initiator name for iSCSI boot. According to the iSCSI RFC (3270) the name has to be UTF-8 encoded, with total length that does not exceed  223 bytes. It allows international characters, but prohibits the use of invisible characters, such as whitespace characters. (Flexboot)


name: value
tlv_name: nv_rom_iscsi_connect_to_first_target
offset: 0x0.24
size: 0x8.0
type: STRING
description:
When the string is "Enabled", Flexboot attempta to connect to the first ISCSI target. Other legal value is "Disabled"


name: value
tlv_name: nv_rom_iscsi_first_target_port
offset: 0x0.24
size: 0x8.0
type: STRING
description:
TCP port for the first iSCSI target (Flexboot)\;Decimal integer in ASCII format up to 5 digits (1-65536).


name: value
tlv_name: nv_rom_iscsi_connect_to_second_target
offset: 0x0.24
size: 0x8.0
type: STRING
description:
When the string is "Enabled", Flexboot attempts to connect to the first ISCSI target. Other legal value is "Disabled"


name: value
tlv_name: nv_rom_iscsi_second_target_port
offset: 0x0.24
size: 0x8.0
type: STRING
description:
TCP port for the second iSCSI target (Flexboot)\;Decimal integer in ASCII format up to 5 digits (1-65536).


name: management_pf
tlv_name: nv_pci_conf
offset: 0x0.10
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,MNG_PF_ENABLE=0x1,MNG_PF_DISABLE=0x2
mlxconfig_name: MANAGEMENT_PF_MODE
dependency: $nv_pci_cap.management_pf_supported != 0
description:
Controls exposing a management networking PF connected directly to the BMC.\;0x0: DEVICE_DEFAULT\;0x1: MNG_PF_ENABLE\;0x2: MNG_PF_DISABLE\;Other values are reserved


name: p2p_ordering_mode
tlv_name: nv_pci_conf
offset: 0x0.12
size: 0x0.2
type: ENUM
textual_values: DEVICE_DEFAULT=0x0,SECURE_NONE=0x1,SECURE_TRUST=0x2,SECURE_ALL=0x3
mlxconfig_name: P2P_ORDERING_MODE
dependency: $nv_pci_cap.p2p_ordering_mode_supported==1
description:
PCI Peer-to-Peer ordering security mode, between read requests completions and writes.\;0x0: DEVICE_DEFAULT\;0x1: SECURE_NONE - no protection/no peer-to-peer\;0x2: SECURE_TRUST - protect untrusted functions\;0x3: SECURE_ALL - protect all functions


name: dynamic_vf_msix
tlv_name: nv_pci_conf
offset: 0x0.23
size: 0x0.1
type: BOOL
mlxconfig_name: DYNAMIC_VF_MSIX_TABLE
dependency: $nv_pci_cap.dynamic_vf_msix_supported!=0
description:
When set to TRUE, the device will support allocation of MSI-Xs to VFs by the PF, after SR-IOV is enabled (while the VF is down).


name: ibm_tunneled_atomic_en
tlv_name: nv_pci_conf
offset: 0x0.27
size: 0x0.1
type: BOOL
mlxconfig_name: IBM_TUNNELED_ATOMIC_EN
dependency: ($nv_pci_cap.ibm_tunneled_atomic_supported!=0)
description:
Enable IBM's Tunneled Atomic feature. Supported only when NV_PCI_CAP.ibm_tunneled_atomic_supported is set.


name: force_eth_subclass
tlv_name: nv_pci_conf
offset: 0x0.29
size: 0x0.1
type: BOOL
mlxconfig_name: FORCE_ETH_PCI_SUBCLASS
description:
Force the PCI function identifier with Ethernet subclass (00h). Supported only when ADVANCED_PCI_SETTINGS is set.

dependency:
($nv_pci_cap.force_eth_subclass_supported!=0)&&($nv_pci_conf.advanced_pci_settings!=0)&&($nv_pci_cap.advanced_pci_settings_supported!=0)


name: ibm_capi_en
tlv_name: nv_pci_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: IBM_CAPI_EN
description:
Enable IBM's Coherent Accelerator Processor Interface (CAPI) mode. Supported only when ADVANCED_PCI_SETTINGS is set.

dependency:
($nv_pci_cap.ibm_capi_supported!=0)&&($nv_pci_conf.advanced_pci_settings!=0)&&($nv_pci_cap.advanced_pci_settings_supported!=0)


name: safe_mode_threshold
tlv_name: safe_mode_conf
offset: 0x0.0
size: 0x0.8
type: UNSIGNED
mlxconfig_name: SAFE_MODE_THRESHOLD
dependency: $safe_mode_conf.safe_mode_enable == 1
description:
Default value of the threshold for failed driver loads (driver load was not detected between reboots). When crossed, the device will load in Safe Mode with some default configurations, suspected as possible causes for driver load fail.


name: safe_mode_enable
tlv_name: safe_mode_conf
offset: 0x0.30
size: 0x0.1
type: BOOL
mlxconfig_name: SAFE_MODE_ENABLE
dependency: ignore_dependency
description:
Enable Safe Mode activation after crossing a threshold of consecutive failed boots (no driver load).


name: priv_level
tlv_name: nv_host_priv_conf
offset: 0x0.28
size: 0x0.2
type: ENUM
textual_values: PRIVILEGED=0x0,LIMITED=0x1
mlxconfig_name: HOST_PRIV_LEVEL
description:
Privilege level of the host\;0x0: PRIVILEGED - host has all supported privileges\;0x1: LIMITED - host is not allowed to modify global/per port/parameters or access other hosts parameters\;\;


